ahoy nice

This commit is contained in:
Nachiket Kapre 2021-02-09 17:38:19 -05:00
parent 71c76df063
commit 4c7f4bd82f
1 changed files with 1 additions and 0 deletions

View File

@ -60,6 +60,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --time_unit ns --flatten_names --file ./SDC
write_pnr_sdc --time_unit ns --flatten_names --hierarchical --file ./SDC_leaf
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc