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[Doc] Update documentation for VPR architectures

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tangxifan 2021-01-12 17:57:40 -07:00
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openfpga_flow/vpr_arch/README.md
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@ -21,5 +21,6 @@ Please reveal the following architecture features in the names to help quickly s
* Top-left (Tl): the pins of a tile are placed on the top side and left side only
* Top-right (Tr): the pins of a tile are placed on the top side and right side only
* Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only
- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks
Other features are used in naming should be listed here.