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[Architecture] Add a new device layout to k4n4 for testing tileable routing

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tangxifan 2020-09-21 18:34:31 -06:00
parent e1c5947143
commit 2bbfcb5753
1 changed files with 7 additions and 0 deletions
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7
openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
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@ -91,6 +91,13 @@
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="4x4" width="6" height="6">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
</layout>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM