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bug fixing for formal top-level testbench

This commit is contained in:
tangxifan 2019-11-01 10:47:40 -06:00
parent d709868463
commit 531cc064fc
4 changed files with 74 additions and 22 deletions
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6
openfpga_flow/tasks/mcnc_big20/config/task.conf
View File

@ -20,7 +20,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem
#arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
[BENCHMARKS]
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
@ -34,8 +34,8 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tem
#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif # Pass
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif # Multi-mode support fails to repack
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif

58
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.cpp
View File

@ -36,6 +36,7 @@ constexpr char* DEFAULT_CLOCK_NAME = "clk";
constexpr char* BENCHMARK_INSTANCE_NAME = "REF_DUT";
constexpr char* FPGA_INSTANCE_NAME = "FPGA_DUT";
constexpr char* ERROR_COUNTER = "nb_error";
constexpr char* FORMAL_TB_SIM_START_PORT_NAME = "sim_start";
constexpr int MAGIC_NUMBER_FOR_SIMULATION_TIME = 200;
/********************************************************************
@ -279,23 +280,29 @@ void print_verilog_timeout_and_vcd(std::fstream& fp,
fp << "\t\t$dumpvars(1, " << circuit_name << FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX << ");" << std::endl;
fp << "\tend" << std::endl;
fp << "\tinitial begin" << std::endl;
fp << "\t\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
fp << "\t\t$display(\"Simulation start\");" << std::endl;
print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------"));
fp << "\t\t#" << simulation_time << std::endl;
fp << "\t\tif(" << ERROR_COUNTER << " == 0) begin" << std::endl;
fp << "\t\t\t$display(\"Simulation Succeed\");" << std::endl;
fp << "\t\tend else begin" << std::endl;
fp << "\t\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << ERROR_COUNTER << ");" << std::endl;
fp << "\t\tend" << std::endl;
fp << "\t\t$finish;" << std::endl;
fp << "\tend" << std::endl;
/* Condition ends for the Icarus requirement */
print_verilog_endif(fp);
print_verilog_comment(fp, std::string("----- END Icarus requirement -------"));
/* Condition ends for the Icarus requirement */
print_verilog_endif(fp);
/* Add an empty line as splitter */
fp << std::endl;
BasicPort sim_start_port(std::string(FORMAL_TB_SIM_START_PORT_NAME), 1);
fp << "initial begin" << std::endl;
fp << "\t" << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << " <= 1'b1;" << std::endl;
fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl;
fp << "\t$display(\"Simulation start\");" << std::endl;
print_verilog_comment(fp, std::string("----- Can be changed by the user for his/her need -------"));
fp << "\t#" << simulation_time << std::endl;
fp << "\tif(" << ERROR_COUNTER << " == 0) begin" << std::endl;
fp << "\t\t$display(\"Simulation Succeed\");" << std::endl;
fp << "\tend else begin" << std::endl;
fp << "\t\t$display(\"Simulation Failed with " << std::string("%d") << " error(s)\", " << ERROR_COUNTER << ");" << std::endl;
fp << "\tend" << std::endl;
fp << "\t$finish;" << std::endl;
fp << "end" << std::endl;
/* Add an empty line as splitter */
fp << std::endl;
@ -321,7 +328,19 @@ void print_verilog_top_random_testbench_check(std::fstream& fp,
BasicPort clock_port = generate_verilog_top_clock_port(clock_port_names);
print_verilog_comment(fp, std::string("----- Skip the first falling edge of clock, it is for initialization -------"));
BasicPort sim_start_port(std::string(FORMAL_TB_SIM_START_PORT_NAME), 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, sim_start_port) << ";" << std::endl;
fp << std::endl;
fp << "\talways@(negedge " << generate_verilog_port(VERILOG_PORT_CONKT, clock_port) << ") begin" << std::endl;
fp << "\t\tif (1'b1 == " << generate_verilog_port(VERILOG_PORT_CONKT, sim_start_port) << ") begin" << std::endl;
fp << "\t\t";
print_verilog_register_connection(fp, sim_start_port, sim_start_port, true);
fp << "\t\tend else begin" << std::endl;
for (const t_logical_block& lb : L_logical_blocks) {
/* Bypass non-I/O logical blocks ! */
if ( (VPACK_INPAD != lb.type) && (VPACK_OUTPAD != lb.type) ) {
@ -329,16 +348,17 @@ void print_verilog_top_random_testbench_check(std::fstream& fp,
}
if (VPACK_OUTPAD == lb.type){
fp << "\t\tif(!(" << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX);
fp << "\t\t\tif(!(" << std::string(lb.name) << std::string(FPGA_PORT_POSTFIX);
fp << " === " << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX);
fp << ") && !(" << std::string(lb.name) << std::string(BENCHMARK_PORT_POSTFIX);
fp << " === 1'bx)) begin" << std::endl;
fp << "\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << " <= 1'b1;" << std::endl;
fp << "\t\tend else begin" << std::endl;
fp << "\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << "<= 1'b0;" << std::endl;
fp << "\t\tend" << std::endl;
fp << "\t\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << " <= 1'b1;" << std::endl;
fp << "\t\t\tend else begin" << std::endl;
fp << "\t\t\t\t" << std::string(lb.name) << std::string(CHECKFLAG_PORT_POSTFIX) << "<= 1'b0;" << std::endl;
fp << "\t\t\tend" << std::endl;
}
}
fp << "\t\tend" << std::endl;
fp << "\tend" << std::endl;
/* Add an empty line as splitter */

27
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
View File

@ -725,6 +725,33 @@ void print_verilog_wire_connection(std::fstream& fp,
fp << ";" << std::endl;
}
/********************************************************************
* Generate a wire connection for two Verilog ports
* using "assign" syntax
*******************************************************************/
void print_verilog_register_connection(std::fstream& fp,
const BasicPort& output_port,
const BasicPort& input_port,
const bool& inverted) {
/* Make sure we have a valid file handler*/
check_file_handler(fp);
/* Must check: the port width matches */
VTR_ASSERT( input_port.get_width() == output_port.get_width() );
fp << "\t";
fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
fp << " <= ";
if (true == inverted) {
fp << "~";
}
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port);
fp << ";" << std::endl;
}
/********************************************************************
* Generate an instance of a buffer module
* with given information about the input and output ports of instance

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h
View File

@ -101,6 +101,11 @@ void print_verilog_wire_connection(std::fstream& fp,
const BasicPort& input_port,
const bool& inverted);
void print_verilog_register_connection(std::fstream& fp,
const BasicPort& output_port,
const BasicPort& input_port,
const bool& inverted);
void print_verilog_buffer_instance(std::fstream& fp,
ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,