Merge remote-tracking branch 'origin/dev' into heterogeneous
This commit is contained in:
commit
feddcbcb21
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@ -18,6 +18,5 @@ end_section "OpenFPGA.build"
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start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
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cd -
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python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
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python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
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python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2
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end_section "OpenFPGA.TaskTun"
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@ -5,7 +5,7 @@
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# Combination of architecture, benchmark and script paramters
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# Args : python3 run_fpga_task.py --help
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# Author : Ganesh Gore
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#Email : ganeshgore@utah.edu
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# Email : ganeshgore@utah.edu
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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import os
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@ -48,6 +48,11 @@ parser.add_argument('tasks', nargs='+')
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parser.add_argument('--maxthreads', type=int, default=2,
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help="Number of fpga_flow threads to run default = 2," +
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"Typically <= Number of processors on the system")
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parser.add_argument('--remove_run_dir', type=str,
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help="Remove run dir " +
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"'all' to remove all." +
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"<int>,<int> to remove specific run dir" +
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"<int>-<int> To remove range of directory")
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parser.add_argument('--config', help="Override default configuration")
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parser.add_argument('--test_run', action="store_true",
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help="Dummy run shows final generated VPR commands")
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@ -84,6 +89,8 @@ def main():
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logger.info("Currently running task %s" % eachtask)
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eachtask = eachtask.replace("\\", "/").split("/")
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job_run_list = generate_each_task_actions(eachtask)
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if args.remove_run_dir:
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continue
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eachtask = "_".join(eachtask)
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if not args.test_run:
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run_actions(job_run_list)
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@ -111,6 +118,40 @@ def validate_command_line_arguments():
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logger.info("Set up to run %d Parallel threads", args.maxthreads)
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def remove_run_dir():
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remove_dir = []
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try:
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argval = args.remove_run_dir.lower()
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if argval == "all":
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for eachRun in glob.glob("run*"):
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remove_dir += [eachRun]
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elif "-" in argval:
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minval, maxval = map(int, argval.split("-"))
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if minval > maxval:
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raise Exception("Enter valid range to remove")
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for eachRun in glob.glob("run*"):
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if minval <= int(eachRun[-3:]) <= maxval:
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remove_dir += [eachRun]
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elif "," in argval:
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for eachRun in argval.split(","):
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remove_dir += ["run%03d" % int(eachRun)]
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else:
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logger.error("Unknow argument to --remove_run_dir")
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except:
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logger.exception("Failed to parse remove rund_dir options")
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try:
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for eachdir in remove_dir:
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logger.info('Removing run_dir %s' % (eachdir))
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if os.path.exists('latest'):
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if eachdir == os.readlink('latest'):
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remove_dir += ["latest"]
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shutil.rmtree(eachdir, ignore_errors=True)
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except:
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logger.exception("Failed to remove %s run directory" %
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(eachdir or "Unknown"))
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def generate_each_task_actions(taskname):
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"""
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This script generates all the scripts required for each benchmark
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@ -130,6 +171,9 @@ def generate_each_task_actions(taskname):
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# Create run directory for current task run ./runxxx
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run_dirs = [int(os.path.basename(x)[-3:]) for x in glob.glob('run*[0-9]')]
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curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1)
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if args.remove_run_dir:
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remove_run_dir()
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return
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try:
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os.mkdir(curr_run_dir)
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if os.path.islink('latest') or os.path.exists('latest'):
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@ -255,7 +299,7 @@ def generate_each_task_actions(taskname):
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"name": "%02d_%s_%s" % (indx, bench["top_module"], lbl),
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"run_dir": flow_run_dir,
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"commands": command,
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"finished" : False,
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"finished": False,
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"status": False})
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logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' %
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@ -383,14 +427,14 @@ def run_single_script(s, eachJob, job_list):
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logger.info("%s Finished with returncode %d, Time Taken %s " %
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(thread_name, process.returncode, timestr))
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eachJob["finished"] = True
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no_of_finished_job = sum([ not eachJ["finished"] for eachJ in job_list])
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no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list])
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logger.info("***** %d runs pending *****" % (no_of_finished_job))
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def run_actions(job_list):
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thread_sema = threading.Semaphore(args.maxthreads)
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thread_list = []
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for _ , eachjob in enumerate(job_list):
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for _, eachjob in enumerate(job_list):
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t = threading.Thread(target=run_single_script, name=eachjob["name"],
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args=(thread_sema, eachjob, job_list))
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t.start()
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@ -33,21 +33,20 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_mode
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
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fix_route_chan_width=300
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vpr_fpga_verilog_include_icarus_simulator=
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vpr_fpga_verilog_formal_verification_top_netlist=
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vpr_fpga_verilog_include_timing=
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vpr_fpga_verilog_include_signal_init=
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vpr_fpga_verilog_print_autocheck_top_testbench=
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vpr_fpga_bitstream_generator=
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vpr_fpga_verilog_print_user_defined_template=
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vpr_fpga_verilog_print_report_timing_tcl=
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vpr_fpga_verilog_print_sdc_pnr=
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vpr_fpga_verilog_print_sdc_analysis=
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#vpr_fpga_x2p_compact_routing_hierarchy=
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end_flow_with_test=
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#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
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#fix_route_chan_width=300
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#vpr_fpga_verilog_include_icarus_simulator=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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#vpr_fpga_verilog_include_timing=
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#vpr_fpga_verilog_include_signal_init=
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#vpr_fpga_verilog_print_autocheck_top_testbench=
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#vpr_fpga_bitstream_generator=
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#vpr_fpga_verilog_print_user_defined_template=
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#vpr_fpga_verilog_print_report_timing_tcl=
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#vpr_fpga_verilog_print_sdc_pnr=
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#vpr_fpga_verilog_print_sdc_analysis=
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##vpr_fpga_x2p_compact_routing_hierarchy=
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#end_flow_with_test=
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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min_route_chan_width=1.3
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@ -1,7 +1,6 @@
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/********************************************************************
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* This file includes functions to
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* generate module/port names for Verilog
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* and SPICE netlists
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* This file includes functions to generate module/port names for
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* Verilog and SPICE netlists
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*
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* IMPORTANT: keep all the naming functions in this file to be
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* generic for both Verilog and SPICE generators
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@ -282,3 +281,23 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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port_name += "_";
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return port_name;
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}
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/*********************************************************************
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* Generate the port name for a reserved sram port, i.e., BLB/WL port
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* When port_type is BLB, a string denoting to the reserved BLB port is generated
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* When port_type is WL, a string denoting to the reserved WL port is generated
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*
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* DO NOT put any SRAM organization check codes HERE!!!
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* Even though the reserved BLB/WL ports are used by RRAM-based FPGA only,
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* try to keep this function does simple job.
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* Check codes should be added outside, when print the ports to files!!!
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*********************************************************************/
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std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type) {
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VTR_ASSERT( (port_type == SPICE_MODEL_PORT_BLB) || (port_type == SPICE_MODEL_PORT_WL) );
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if (SPICE_MODEL_PORT_BLB == port_type) {
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return std::string("reserved_blb");
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}
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return std::string("reserved_wl");
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}
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@ -67,4 +67,6 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
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const size_t& pin_id,
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const bool& for_top_netlist);
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std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type);
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#endif
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@ -12,6 +12,9 @@
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#include "circuit_library.h"
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#include "module_manager.h"
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#include "fpga_x2p_naming.h"
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#include "module_manager_utils.h"
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/******************************************************************************
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@ -72,3 +75,35 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
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return add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model, circuit_lib.model_name(circuit_model));
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}
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/********************************************************************
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* Add a list of ports that are used for reserved SRAM ports to a module
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* in the module manager
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* The reserved SRAM ports are mainly designed for RRAM-based FPGA,
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* which are shared across modules.
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* Note that different modules may require different size of reserved
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* SRAM ports but their LSB must all start from 0
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* +---------+
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* reserved_sram_port[0:X] --->| ModuleA |
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* +---------+
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*
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* +---------+
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* reserved_sram_port[0:Y] --->| ModuleB |
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* +---------+
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*
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********************************************************************/
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void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager,
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const ModuleId& module_id,
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const size_t& port_size) {
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/* Add a reserved BLB port to the module */
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std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB);
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BasicPort blb_module_port(blb_port_name, port_size);
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/* Add generated ports to the ModuleManager */
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module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT);
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/* Add a reserved BLB port to the module */
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std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL);
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BasicPort wl_module_port(wl_port_name, port_size);
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/* Add generated ports to the ModuleManager */
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module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT);
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}
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@ -7,6 +7,8 @@
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#define MODULE_MANAGER_UTILS_H
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/* Include other header files which are dependency on the function declared below */
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#include <vector>
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#include "device_port.h"
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#include "circuit_library.h"
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#include "module_manager.h"
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@ -17,5 +19,9 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
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ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model);
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void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager,
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const ModuleId& module_id,
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const size_t& port_size);
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#endif
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@ -36,7 +36,7 @@ std::vector<CircuitPortId> find_switch_block_global_ports(const RRGSB& rr_gsb,
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/* Get the model, and try to add to the sub_model list */
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CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model;
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/* Make sure it is a valid id */
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VTR_ASSERT( CircuitModelId::INVALID() == switch_circuit_model );
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VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model );
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/* Get the model, and try to add to the sub_model list */
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if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) {
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/* Not yet in the list, add it */
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@ -39,6 +39,8 @@
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#include "fpga_x2p_bitstream_utils.h"
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#include "fpga_x2p_globals.h"
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#include "fpga_x2p_naming.h"
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#include "module_manager.h"
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#include "module_manager_utils.h"
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/* Include Verilog support headers*/
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#include "verilog_global.h"
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@ -2278,16 +2280,14 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
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}
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/* Add configuration ports */
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/* TODO: Reserved sram ports */
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/*
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/* Reserved sram ports */
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if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
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dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
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rr_gsb.get_sb_reserved_conf_bits_lsb(),
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rr_gsb.get_sb_reserved_conf_bits_msb(),
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VERILOG_PORT_INPUT);
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fprintf(fp, ",\n");
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/* Check: this SRAM organization type must be memory-bank ! */
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VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type );
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/* Generate a list of ports */
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add_reserved_sram_ports_to_module_manager(module_manager, module_id,
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rr_gsb.get_sb_num_reserved_conf_bits());
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}
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*/
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/* TODO: Normal sram ports */
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/*
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dump_verilog_sram_ports(fp, cur_sram_orgz_info,
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@ -2311,6 +2311,10 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
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fprintf(fp, "); \n");
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*/
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/* Print module definition + ports */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Finish printing ports */
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/* TODO: Local wires for memory configurations */
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/*
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dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
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|
@ -4143,13 +4147,11 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
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const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
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dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir,
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subckt_dir, unique_mirror, explicit_port_mapping);
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/*
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print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib,
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rr_switches,
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cur_sram_orgz_info, std::string(verilog_dir),
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std::string(subckt_dir), unique_mirror,
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explicit_port_mapping);
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*/
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}
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/* Restore sram_orgz_info to the base */
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|
|
|
@ -105,8 +105,8 @@ void print_verilog_module_definition(std::fstream& fp,
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std::string port_whitespace(module_head_line.length(), ' ');
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fp << port_whitespace;
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}
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/* Print port */
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fp << generate_verilog_port(kv.second, port);
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/* Print port: only the port name is enough */
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fp << port.get_name();
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port_cnt++;
|
||||
}
|
||||
}
|
||||
|
|
Loading…
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