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OpenFPGA
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Merge remote-tracking branch 'origin/dev' into heterogeneous

This commit is contained in:
AurelienUoU 2019-09-23 11:41:38 -06:00
parent cc0bfdd548 d2ddbc19a3
commit feddcbcb21
10 changed files with 143 additions and 37 deletions
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3
.travis/script.sh
View File

@ -18,6 +18,5 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2
end_section "OpenFPGA.TaskTun"

52
openfpga_flow/scripts/run_fpga_task.py
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@ -5,7 +5,7 @@
# Combination of architecture, benchmark and script paramters
# Args : python3 run_fpga_task.py --help
# Author : Ganesh Gore
#Email : ganeshgore@utah.edu
# Email : ganeshgore@utah.edu
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
import os
@ -48,6 +48,11 @@ parser.add_argument('tasks', nargs='+')
parser.add_argument('--maxthreads', type=int, default=2,
help="Number of fpga_flow threads to run default = 2," +
"Typically <= Number of processors on the system")
parser.add_argument('--remove_run_dir', type=str,
help="Remove run dir " +
"'all' to remove all." +
"<int>,<int> to remove specific run dir" +
"<int>-<int> To remove range of directory")
parser.add_argument('--config', help="Override default configuration")
parser.add_argument('--test_run', action="store_true",
help="Dummy run shows final generated VPR commands")
@ -84,6 +89,8 @@ def main():
logger.info("Currently running task %s" % eachtask)
eachtask = eachtask.replace("\\", "/").split("/")
job_run_list = generate_each_task_actions(eachtask)
if args.remove_run_dir:
continue
eachtask = "_".join(eachtask)
if not args.test_run:
run_actions(job_run_list)
@ -111,6 +118,40 @@ def validate_command_line_arguments():
logger.info("Set up to run %d Parallel threads", args.maxthreads)
def remove_run_dir():
remove_dir = []
try:
argval = args.remove_run_dir.lower()
if argval == "all":
for eachRun in glob.glob("run*"):
remove_dir += [eachRun]
elif "-" in argval:
minval, maxval = map(int, argval.split("-"))
if minval > maxval:
raise Exception("Enter valid range to remove")
for eachRun in glob.glob("run*"):
if minval <= int(eachRun[-3:]) <= maxval:
remove_dir += [eachRun]
elif "," in argval:
for eachRun in argval.split(","):
remove_dir += ["run%03d" % int(eachRun)]
else:
logger.error("Unknow argument to --remove_run_dir")
except:
logger.exception("Failed to parse remove rund_dir options")
try:
for eachdir in remove_dir:
logger.info('Removing run_dir %s' % (eachdir))
if os.path.exists('latest'):
if eachdir == os.readlink('latest'):
remove_dir += ["latest"]
shutil.rmtree(eachdir, ignore_errors=True)
except:
logger.exception("Failed to remove %s run directory" %
(eachdir or "Unknown"))
def generate_each_task_actions(taskname):
"""
This script generates all the scripts required for each benchmark
@ -130,6 +171,9 @@ def generate_each_task_actions(taskname):
# Create run directory for current task run ./runxxx
run_dirs = [int(os.path.basename(x)[-3:]) for x in glob.glob('run*[0-9]')]
curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1)
if args.remove_run_dir:
remove_run_dir()
return
try:
os.mkdir(curr_run_dir)
if os.path.islink('latest') or os.path.exists('latest'):
@ -255,7 +299,7 @@ def generate_each_task_actions(taskname):
"name": "%02d_%s_%s" % (indx, bench["top_module"], lbl),
"run_dir": flow_run_dir,
"commands": command,
"finished" : False,
"finished": False,
"status": False})
logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' %
@ -383,14 +427,14 @@ def run_single_script(s, eachJob, job_list):
logger.info("%s Finished with returncode %d, Time Taken %s " %
(thread_name, process.returncode, timestr))
eachJob["finished"] = True
no_of_finished_job = sum([ not eachJ["finished"] for eachJ in job_list])
no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list])
logger.info("***** %d runs pending *****" % (no_of_finished_job))
def run_actions(job_list):
thread_sema = threading.Semaphore(args.maxthreads)
thread_list = []
for _ , eachjob in enumerate(job_list):
for _, eachjob in enumerate(job_list):
t = threading.Thread(target=run_single_script, name=eachjob["name"],
args=(thread_sema, eachjob, job_list))
t.start()

29
openfpga_flow/tasks/blif_vpr_flow/config/task.conf
View File

@ -33,21 +33,20 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_mode
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
bench0_chan_width = 300
[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
fix_route_chan_width=300
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=
#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
#fix_route_chan_width=300
#vpr_fpga_verilog_include_icarus_simulator=
#vpr_fpga_verilog_formal_verification_top_netlist=
#vpr_fpga_verilog_include_timing=
#vpr_fpga_verilog_include_signal_init=
#vpr_fpga_verilog_print_autocheck_top_testbench=
#vpr_fpga_bitstream_generator=
#vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
##vpr_fpga_x2p_compact_routing_hierarchy=
#end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
min_route_chan_width=1.3

25
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -1,7 +1,6 @@
/********************************************************************
* This file includes functions to
* generate module/port names for Verilog
* and SPICE netlists
* This file includes functions to generate module/port names for
* Verilog and SPICE netlists
*
* IMPORTANT: keep all the naming functions in this file to be
* generic for both Verilog and SPICE generators
@ -282,3 +281,23 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
port_name += "_";
return port_name;
}
/*********************************************************************
* Generate the port name for a reserved sram port, i.e., BLB/WL port
* When port_type is BLB, a string denoting to the reserved BLB port is generated
* When port_type is WL, a string denoting to the reserved WL port is generated
*
* DO NOT put any SRAM organization check codes HERE!!!
* Even though the reserved BLB/WL ports are used by RRAM-based FPGA only,
* try to keep this function does simple job.
* Check codes should be added outside, when print the ports to files!!!
*********************************************************************/
std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type) {
VTR_ASSERT( (port_type == SPICE_MODEL_PORT_BLB) || (port_type == SPICE_MODEL_PORT_WL) );
if (SPICE_MODEL_PORT_BLB == port_type) {
return std::string("reserved_blb");
}
return std::string("reserved_wl");
}

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.h
View File

@ -67,4 +67,6 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
const size_t& pin_id,
const bool& for_top_netlist);
std::string generate_reserved_sram_port_name(const e_spice_model_port_type& port_type);
#endif

35
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.cpp
View File

@ -12,6 +12,9 @@
#include "circuit_library.h"
#include "module_manager.h"
#include "fpga_x2p_naming.h"
#include "module_manager_utils.h"
/******************************************************************************
@ -72,3 +75,35 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
return add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model, circuit_lib.model_name(circuit_model));
}
/********************************************************************
* Add a list of ports that are used for reserved SRAM ports to a module
* in the module manager
* The reserved SRAM ports are mainly designed for RRAM-based FPGA,
* which are shared across modules.
* Note that different modules may require different size of reserved
* SRAM ports but their LSB must all start from 0
* +---------+
* reserved_sram_port[0:X] --->| ModuleA |
* +---------+
*
* +---------+
* reserved_sram_port[0:Y] --->| ModuleB |
* +---------+
*
********************************************************************/
void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager,
const ModuleId& module_id,
const size_t& port_size) {
/* Add a reserved BLB port to the module */
std::string blb_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_BLB);
BasicPort blb_module_port(blb_port_name, port_size);
/* Add generated ports to the ModuleManager */
module_manager.add_port(module_id, blb_module_port, ModuleManager::MODULE_INPUT_PORT);
/* Add a reserved BLB port to the module */
std::string wl_port_name = generate_reserved_sram_port_name(SPICE_MODEL_PORT_WL);
BasicPort wl_module_port(wl_port_name, port_size);
/* Add generated ports to the ModuleManager */
module_manager.add_port(module_id, wl_module_port, ModuleManager::MODULE_INPUT_PORT);
}

6
vpr7_x2p/vpr/SRC/fpga_x2p/base/module_manager_utils.h
View File

@ -7,6 +7,8 @@
#define MODULE_MANAGER_UTILS_H
/* Include other header files which are dependency on the function declared below */
#include <vector>
#include "device_port.h"
#include "circuit_library.h"
#include "module_manager.h"
@ -17,5 +19,9 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model);
void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager,
const ModuleId& module_id,
const size_t& port_size);
#endif

2
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_utils.cpp
View File

@ -36,7 +36,7 @@ std::vector<CircuitPortId> find_switch_block_global_ports(const RRGSB& rr_gsb,
/* Get the model, and try to add to the sub_model list */
CircuitModelId switch_circuit_model = switch_lib[driver_switch].circuit_model;
/* Make sure it is a valid id */
VTR_ASSERT( CircuitModelId::INVALID() == switch_circuit_model );
VTR_ASSERT( CircuitModelId::INVALID() != switch_circuit_model );
/* Get the model, and try to add to the sub_model list */
if (sub_models.end() == std::find(sub_models.begin(), sub_models.end(), switch_circuit_model)) {
/* Not yet in the list, add it */

22
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -39,6 +39,8 @@
#include "fpga_x2p_bitstream_utils.h"
#include "fpga_x2p_globals.h"
#include "fpga_x2p_naming.h"
#include "module_manager.h"
#include "module_manager_utils.h"
/* Include Verilog support headers*/
#include "verilog_global.h"
@ -2278,16 +2280,14 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
}
/* Add configuration ports */
/* TODO: Reserved sram ports */
/*
/* Reserved sram ports */
if (0 < rr_sb.get_sb_num_reserved_conf_bits()) {
dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
rr_gsb.get_sb_reserved_conf_bits_lsb(),
rr_gsb.get_sb_reserved_conf_bits_msb(),
VERILOG_PORT_INPUT);
fprintf(fp, ",\n");
/* Check: this SRAM organization type must be memory-bank ! */
VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type );
/* Generate a list of ports */
add_reserved_sram_ports_to_module_manager(module_manager, module_id,
rr_gsb.get_sb_num_reserved_conf_bits());
}
*/
/* TODO: Normal sram ports */
/*
dump_verilog_sram_ports(fp, cur_sram_orgz_info,
@ -2311,6 +2311,10 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage
fprintf(fp, "); \n");
*/
/* Print module definition + ports */
print_verilog_module_declaration(fp, module_manager, module_id);
/* Finish printing ports */
/* TODO: Local wires for memory configurations */
/*
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
@ -4143,13 +4147,11 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
dump_verilog_routing_switch_box_unique_subckt(cur_sram_orgz_info, verilog_dir,
subckt_dir, unique_mirror, explicit_port_mapping);
/*
print_verilog_routing_switch_box_unique_module(module_manager, arch.spice->circuit_lib, mux_lib,
rr_switches,
cur_sram_orgz_info, std::string(verilog_dir),
std::string(subckt_dir), unique_mirror,
explicit_port_mapping);
*/
}
/* Restore sram_orgz_info to the base */

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp
View File

@ -105,8 +105,8 @@ void print_verilog_module_definition(std::fstream& fp,
std::string port_whitespace(module_head_line.length(), ' ');
fp << port_whitespace;
}
/* Print port */
fp << generate_verilog_port(kv.second, port);
/* Print port: only the port name is enough */
fp << port.get_name();
port_cnt++;
}
}