fine tuning on the script for MCNC benchmarks

openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga

@@ -48,7 +48,7 @@ write_fabric_verilog --file ./SRC \
   --explicit_port_mapping \
   --include_timing \
   --include_signal_init
-  #--support_icarus_simulator
+# --support_icarus_simulator
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists