[Architecture] Bug fix in configurable latch Verilog HDL
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@ -17,7 +17,7 @@ module config_latch (
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge reset) begin
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always @ (reset or bl or wl) begin
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if (reset) begin
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q_reg <= 1'b0;
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end else if (1'b1 == wl) begin
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@ -12,7 +12,7 @@ input WE, // Write Enable
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input CK, // Clock Input
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/* Local ports follow */
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input D, // Data Input
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output Q // Q output
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output Q, // Q output
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output QB // QB output
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);
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//------------Internal Variables--------
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@ -20,7 +20,7 @@ reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RESET) begin
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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@ -146,7 +146,7 @@
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<port type="sram" prefix="sram" size="16"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="sram" name="DFF_EN" prefix="DFF_EN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/DFF_EN.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/DFF_EN.v">
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<circuit_model type="sram" name="DFF_EN" prefix="DFF_EN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff_en.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff_en.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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