[Architecture] Bug fix in configurable latch Verilog HDL

This commit is contained in:
tangxifan 2020-09-23 18:28:45 -06:00
parent 9adeb550dc
commit 1864b080a2
3 changed files with 4 additions and 4 deletions

View File

@ -17,7 +17,7 @@ module config_latch (
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge reset) begin
always @ (reset or bl or wl) begin
if (reset) begin
q_reg <= 1'b0;
end else if (1'b1 == wl) begin

View File

@ -12,7 +12,7 @@ input WE, // Write Enable
input CK, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q // Q output
output Q, // Q output
output QB // QB output
);
//------------Internal Variables--------
@ -20,7 +20,7 @@ reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RESET) begin
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;

View File

@ -146,7 +146,7 @@
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sram" name="DFF_EN" prefix="DFF_EN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/DFF_EN.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/DFF_EN.v">
<circuit_model type="sram" name="DFF_EN" prefix="DFF_EN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff_en.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff_en.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>