41 lines
943 B
Verilog
41 lines
943 B
Verilog
//-----------------------------------------------------
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// Design Name : D-type Flip-flop with Write Enable
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// File Name : ff_en.v
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// Function : D flip-flop with asyn reset and set
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// Coder : Xifan TANG
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//-----------------------------------------------------
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module DFF_EN (
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/* Global ports go first */
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input SET, // set input
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input RST, // Reset input
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input WE, // Write Enable
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input CK, // Clock Input
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/* Local ports follow */
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input D, // Data Input
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output Q, // Q output
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output QB // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else if (WE) begin
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q_reg <= D;
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end
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`ifndef ENABLE_FORMAL_VERIFICATION
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// Wire q_reg to Q
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assign Q = q_reg;
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assign QB = ~q_reg;
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`else
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assign Q = 1'bZ;
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assign QB = !Q;
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`endif
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endmodule //End Of Module
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