3 Commits

Author	SHA1	Message	Date
tangxifan	1864b080a2	[Architecture] Bug fix in configurable latch Verilog HDL	2020-09-23 18:28:45 -06:00
tangxifan	645db17168	[Architecture] Patch DFF Verilog HDL	2020-09-23 17:52:59 -06:00
tangxifan	092ada39f4	[Architecture] Add Verilog HDL for DFF with write enable	2020-09-23 17:49:30 -06:00