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[Architecture] Merge latch Verilog HDL to a unique file

This commit is contained in:
tangxifan 2020-09-24 11:02:01 -06:00
parent 48083d2276
commit 7238a2be03
6 changed files with 255 additions and 189 deletions
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37
openfpga_flow/VerilogNetlists/config_latch.v
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@ -1,37 +0,0 @@
//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated when wl is enabled
// Reset is active high
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch (
input reset, // Reset input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (reset or bl or wl) begin
if (reset) begin
q_reg <= 1'b0;
end else if (1'b1 == wl) begin
q_reg <= bl;
end
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule

37
openfpga_flow/VerilogNetlists/config_latch_neg_rst.v
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@ -1,37 +0,0 @@
//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated when wl is enabled
// Reset is active low
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch (
input resetb, // Reset input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (resetb or wl or bl) begin
if (~resetb) begin
q_reg <= 1'b0;
end else if (1'b1 == wl) begin
q_reg <= bl;
end
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule

37
openfpga_flow/VerilogNetlists/config_latch_neg_set.v
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@ -1,37 +0,0 @@
//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated when wl is enabled
// Reset is active low
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch_neg_set (
input setb, // Reset input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (setb or wl or bl) begin
if (~setb) begin
q_reg <= 1'b1;
end else if (1'b1 == wl) begin
q_reg <= bl;
end
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule

37
openfpga_flow/VerilogNetlists/config_latch_set.v
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@ -1,37 +0,0 @@
//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated when wl is enabled
// Set is active high
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch_set (
input set, // Reset input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (set or bl or wl) begin
if (set) begin
q_reg <= 1'b1;
end else if (1'b1 == wl) begin
q_reg <= bl;
end
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule

41
openfpga_flow/VerilogNetlists/config_latch_set_reset.v
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@ -1,41 +0,0 @@
//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Function : A Configurable Latch where data storage
// can be updated when wl is enabled
// Reset is active high
// Set is active high
// Coder : Xifan TANG
//-----------------------------------------------------
module config_latch_set_reset (
input reset, // Reset input
input set, // Set input
input wl, // Data Enable
input bl, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (reset or set or bl or wl) begin
if (reset) begin
q_reg <= 1'b0;
end else if (set) begin
q_reg <= 1'b1;
end else if (1'b1 == wl) begin
q_reg <= bl;
end
end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule

255
openfpga_flow/VerilogNetlists/latch.v Normal file
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@ -0,0 +1,255 @@
//-----------------------------------------------------
// Design Name : config_latch
// File Name : config_latch.v
// Coder : Xifan TANG
//-----------------------------------------------------
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
//-----------------------------------------------------
module LATCH (
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (WE or D) begin
if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
// - an active-high reset signal
//-----------------------------------------------------
module LATCHR (
input RST, // Reset signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (RST or WE or D) begin
if (RST) begin
q_reg <= 1'b0;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
// - an active-low reset signal
//-----------------------------------------------------
module LATCHRN (
input RSTN, // Reset signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (RSTN or WE or D) begin
if (~RSTN) begin
q_reg <= 1'b0;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
// - an active-high set signal
//-----------------------------------------------------
module LATCHS (
input SET, // Set signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (SET or WE or D) begin
if (SET) begin
q_reg <= 1'b1;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
// - an active-low set signal
//-----------------------------------------------------
module LATCHSN (
input SETN, // Set signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (SETN or WE or D) begin
if (~SETN) begin
q_reg <= 1'b1;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
// - an active-high reset signal
// - an active-high set signal
//-----------------------------------------------------
module LATCHSR (
input RST, // Reset signal
input SET, // Set signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (RST or SET or WE or D) begin
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule
//-----------------------------------------------------
// Function : A Configurable Latch with
// - an active-high write enable signal
// - an active-high reset signal
// - an active-high set signal
//-----------------------------------------------------
module LATCHSNRN (
input RSTN, // Reset signal
input SETN, // Set signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (RSTN or SETN or WE or D) begin
if (~RSTN) begin
q_reg <= 1'b0;
end else if (~SETN) begin
q_reg <= 1'b1;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule