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[Arch] Remove port size XML syntax

This commit is contained in:
tangxifan 2021-01-09 16:30:46 -07:00
parent 9f12b25a24
commit 7b24da267a
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
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@ -169,7 +169,7 @@
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<global_port name="clk" size="1" is_clock="true" default_val="0">
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
</global_port>
</tile_annotations>