From 7b24da267a6077584c1fc87745a00c953c1c657c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 9 Jan 2021 16:30:46 -0700
Subject: [PATCH] [Arch] Remove port size XML syntax

---
 .../openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
index bf936700e..ed9abccff 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
@@ -169,7 +169,7 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <tile_annotations>
-    <global_port name="clk" size="1" is_clock="true" default_val="0">
+    <global_port name="clk" is_clock="true" default_val="0">
       <tile name="clb" port="clk" x="-1" y="-1"/>
     </global_port>
   </tile_annotations>