[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals

This commit is contained in:
tangxifan 2020-11-22 20:53:32 -07:00
parent fd0e6814ea
commit 5eb04e6fff
1 changed files with 6 additions and 4 deletions

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@ -7,10 +7,12 @@
//-----------------------------------------------------
module MUX2(
input A, // Data input 0
input B, // Data input 1
input S0, // Select port
output Y // Data output
// iVerilog is buggy on the 'input A' declaration when deposit initial
// values
input [0:0] A, // Data input 0
input [0:0] B, // Data input 1
input [0:0] S0, // Select port
output [0:0] Y // Data output
);
assign Y = S0 ? B : A;