[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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@ -7,10 +7,12 @@
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//-----------------------------------------------------
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module MUX2(
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input A, // Data input 0
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input B, // Data input 1
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input S0, // Select port
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output Y // Data output
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// iVerilog is buggy on the 'input A' declaration when deposit initial
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// values
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input [0:0] A, // Data input 0
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input [0:0] B, // Data input 1
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input [0:0] S0, // Select port
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output [0:0] Y // Data output
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);
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assign Y = S0 ? B : A;
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