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[Architecture] Bug fix for standalone memory

This commit is contained in:
tangxifan 2020-09-23 19:32:48 -06:00
parent 437ef54431
commit 8e4e66038a
1 changed files with 0 additions and 1 deletions
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openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml
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@ -155,7 +155,6 @@
<port type="wl" prefix="wl" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>