add a flagship architecture using fracturable memory and dsp
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tangxifan
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cfd035bf8f
commit
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
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<design_technology type="cmos" topology="OR"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="a b" out_port="out">
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10e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
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<design_technology type="cmos" fracturable_lut="true"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
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<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
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<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
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<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
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<port type="sram" prefix="sram" size="64"/>
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="Qb" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
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<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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<port type="input" prefix="outpad" size="1"/>
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<port type="output" prefix="inpad" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="a" size="1"/>
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<port type="input" prefix="b" size="1"/>
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<port type="input" prefix="cin" size="1"/>
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<port type="output" prefix="sumout" size="1"/>
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<port type="output" prefix="cout" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="mult_36x36" prefix="mult_36x36" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_36x36.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_36x36.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="a" size="36"/>
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<port type="input" prefix="b" size="36"/>
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<port type="output" prefix="out" size="72"/>
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<!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
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<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="frac_mem_32k" prefix="frac_mem_32k" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/frac_mem_32k.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/frac_mem_32k.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="addr1" lib_name="addr_a" size="15"/>
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<port type="input" prefix="addr2" lib_name="addr_b" size="15"/>
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<port type="input" prefix="data1" lib_name="data_a" size="32"/>
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<port type="input" prefix="data2" lib_name="data_b" size="32"/>
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<port type="input" prefix="we1" lib_name="we_a" size="1"/>
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<port type="input" prefix="we2" lib_name="we_b" size="1"/>
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<port type="output" prefix="out1" lib_name="q_a" size="32"/>
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<port type="output" prefix="out2" lib_name="q_b" size="32"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
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<!-- As a fracturable memory, it requires 4 configuration bits to operate in 13 different modes -->
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<port type="sram" prefix="mode" size="4" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<direct_connection>
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<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb">
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<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
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<interconnect name="crossbar" circuit_model_name="mux_2level"/>
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</pb_type>
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
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<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
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<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
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<!-- Binding operating pb_type to physical pb_type -->
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<!-- Binding operating pb_types in mode 'n2_lut5' -->
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<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
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<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:4]"/>
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<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- Binding operating pb_types in mode 'arithmetic' -->
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<pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
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<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
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</pb_type>
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<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
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<pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- Binding operating pb_types in mode 'ble6' -->
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
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<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
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<port name="in" physical_mode_port="in[0:5]"/>
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<port name="out" physical_mode_port="lut6_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
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<!-- End physical pb_type binding in complex block clb -->
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<!-- physical pb_type binding in complex block dsp -->
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<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
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<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
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<pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/>
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<!-- Bind the 9x9 multiplier to the physical 36x36 multiplier
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There are four 9x9 multipliers, each of which occupies part
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of the input/output of the 36x36 multiplier
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-->
|
||||
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
|
||||
<port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
|
||||
<port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 18x18 multiplier to the physical 36x36 multiplier
|
||||
There are two 18x18 multipliers, each of which occupies part
|
||||
of the input/output of the 36x36 multiplier
|
||||
-->
|
||||
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
|
||||
</pb_type>
|
||||
<!-- END physical pb_type binding in complex block dsp -->
|
||||
|
||||
<!-- physical pb_type binding in complex block memory -->
|
||||
<pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/>
|
||||
<pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/>
|
||||
<!-- Bind the 512x64 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
|
||||
<port name="addr" physical_mode_port="addr1[0:8]"/>
|
||||
<port name="data" physical_mode_port="data1 data2"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1 out2"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 1024x32 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
|
||||
<port name="addr" physical_mode_port="addr1[0:9]"/>
|
||||
<port name="data" physical_mode_port="data1"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 2048x16 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
|
||||
<port name="addr" physical_mode_port="addr1[0:10]"/>
|
||||
<port name="data" physical_mode_port="data1[0:15]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:15]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 4096x8 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
|
||||
<port name="addr" physical_mode_port="addr1[0:11]"/>
|
||||
<port name="data" physical_mode_port="data1[0:7]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:7]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 8192x4 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
|
||||
<port name="addr" physical_mode_port="addr1[0:12]"/>
|
||||
<port name="data" physical_mode_port="data1[0:3]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:3]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 16384x2 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
|
||||
<port name="addr" physical_mode_port="addr1[0:13]"/>
|
||||
<port name="data" physical_mode_port="data1[0:1]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:1]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 32768x1 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
|
||||
<port name="addr" physical_mode_port="addr1[0:14]"/>
|
||||
<port name="data" physical_mode_port="data1[0:0]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:0]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 1024x32 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
|
||||
<port name="addr1" physical_mode_port="addr1[0:9]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:9]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:31]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:31]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:31]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:31]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 1024x32 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0111">
|
||||
<port name="addr1" physical_mode_port="addr1[0:9]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:9]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:31]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:31]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:31]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:31]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 2048x16 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
|
||||
<port name="addr1" physical_mode_port="addr1[0:10]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:10]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:15]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:15]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:15]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:15]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 4096x8 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
|
||||
<port name="addr1" physical_mode_port="addr1[0:11]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:11]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:7]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:7]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:7]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:7]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 8192x4 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
|
||||
<port name="addr1" physical_mode_port="addr1[0:12]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:12]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:3]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:3]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:3]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:3]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 16384x2 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
|
||||
<port name="addr1" physical_mode_port="addr1[0:13]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:13]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:1]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:1]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:1]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:1]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 32768x1 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
|
||||
<port name="addr1" physical_mode_port="addr1[0:14]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:14]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:0]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:0]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:0]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:0]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- END physical pb_type binding in complex block memory -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue