update tutorials about the verilog-to-verification

docs/source/tutorials/design_flow/index.rst

@@ -7,6 +7,6 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
-   blif_to_verification
+   verilog2verification
 
-   verilog_to_gds2
+   verilog2gds2

docs/source/tutorials/design_flow/verilog2verification.rst

@@ -1,7 +1,7 @@
-.. _from_blif_to_verification:
+.. _from_verilog_to_verification:
 
-From BLIF to Verification
--------------------------
+From Verilog to Verification
+----------------------------
 
 This tutorial will show an example how to 
   - generate Verilog netlists for a FPGA fabric