From cfd035bf8f3a0c65634c02ffeff4373ef8012656 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Aug 2020 14:33:51 -0600 Subject: [PATCH] update tutorials about the verilog-to-verification --- docs/source/tutorials/design_flow/index.rst | 4 ++-- .../design_flow/{verilog_to_gds2.rst => verilog2gds2.rst} | 0 .../{blif_to_verification.rst => verilog2verification.rst} | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) rename docs/source/tutorials/design_flow/{verilog_to_gds2.rst => verilog2gds2.rst} (100%) rename docs/source/tutorials/design_flow/{blif_to_verification.rst => verilog2verification.rst} (98%) diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst index e854a08c6..82a9ed3e4 100644 --- a/docs/source/tutorials/design_flow/index.rst +++ b/docs/source/tutorials/design_flow/index.rst @@ -7,6 +7,6 @@ Design Flows .. toctree:: :maxdepth: 2 - blif_to_verification + verilog2verification - verilog_to_gds2 + verilog2gds2 diff --git a/docs/source/tutorials/design_flow/verilog_to_gds2.rst b/docs/source/tutorials/design_flow/verilog2gds2.rst similarity index 100% rename from docs/source/tutorials/design_flow/verilog_to_gds2.rst rename to docs/source/tutorials/design_flow/verilog2gds2.rst diff --git a/docs/source/tutorials/design_flow/blif_to_verification.rst b/docs/source/tutorials/design_flow/verilog2verification.rst similarity index 98% rename from docs/source/tutorials/design_flow/blif_to_verification.rst rename to docs/source/tutorials/design_flow/verilog2verification.rst index 26a0b87cf..505aa39c7 100644 --- a/docs/source/tutorials/design_flow/blif_to_verification.rst +++ b/docs/source/tutorials/design_flow/verilog2verification.rst @@ -1,7 +1,7 @@ -.. _from_blif_to_verification: +.. _from_verilog_to_verification: -From BLIF to Verification -------------------------- +From Verilog to Verification +---------------------------- This tutorial will show an example how to - generate Verilog netlists for a FPGA fabric