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[Architecture] Bug fix for scan-chain FF cell renaming

This commit is contained in:
tangxifan 2020-09-24 17:33:14 -06:00
parent 0a5369f919
commit 49d6863641
4 changed files with 15 additions and 18 deletions
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9
openfpga_flow/VerilogNetlists/dff.v
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@ -244,15 +244,14 @@ endmodule //End Of Module
// - scan-chain input
// - a scan-chain enable
//-----------------------------------------------------
module SDFFSR (
module SDFFSRQ (
input SET, // Set input
input RST, // Reset input
input SE, // Scan-chain Enable
input SI, // Scan-chain input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
@ -272,10 +271,8 @@ end
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule //End Of Module

8
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
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@ -142,13 +142,13 @@
This is flip-flop with scan-chain feature.
When the TESTEN is enabled, the data will be propagated form DI instead of D
-->
<circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
<circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" size="1"/>
<port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="DI" lib_name="SI" size="1"/>
<port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
@ -233,7 +233,7 @@
</pb_type>
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' -->

6
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
View File

@ -142,13 +142,13 @@
This is flip-flop with scan-chain feature.
When the TESTEN is enabled, the data will be propagated form DI instead of D
-->
<circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
<circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="D_chain" lib_name="DI" size="1"/>
<port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
@ -228,7 +228,7 @@
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' -->

10
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -142,13 +142,13 @@
This is flip-flop with scan-chain feature.
When the TESTEN is enabled, the data will be propagated form DI instead of D
-->
<circuit_model type="ff" name="scan_chain_ff" prefix="scan_chain_ff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
<circuit_model type="ff" name="SDFFSRQ" prefix="SDFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="D_chain" lib_name="DI" size="1"/>
<port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="TESTEN" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
@ -243,7 +243,7 @@
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' -->
@ -278,7 +278,7 @@
<!-- Binding regular FLEs -->
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' -->
@ -311,7 +311,7 @@
<pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/>
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="SDFFSRQ"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'n2_lut5' -->