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Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev

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Ganesh Gore 2019-11-01 00:46:34 -06:00
parent 81180939ca d709868463
commit da0778e813
213 changed files with 189680 additions and 3477 deletions
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41
.travis.yml
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@ -22,6 +22,7 @@ matrix:
- os: linux
# Compiler is specified in ./travis/common.sh
sudo: false
dist: bionic
compiler: g++-8
addons:
apt:
@ -42,8 +43,6 @@ matrix:
- fontconfig
- g++-8
- gcc-8
- g++-4.9
- gcc-4.9
- gdb
- git
- gperf
@ -63,25 +62,25 @@ matrix:
- valgrind
- zip
- qt5-default
- os: osx
osx_image: xcode10.2 # we target latest MacOS Mojave
sudo: true
compiler: gcc-4.9 # Use clang instead of gcc in MacOS
addons:
homebrew:
packages:
- bison
- cmake
- ctags
- flex
- fontconfig
- git
- gcc@6
- gcc@4.9
- gawk
- icarus-verilog
- libxml++
- qt5
# - os: osx
# osx_image: xcode10.2 # we target latest MacOS Mojave
# sudo: true
# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
# addons:
# homebrew:
# packages:
# - bison
# - cmake
# - ctags
# - flex
# - fontconfig
# - git
# - gcc@6
# - gcc@4.9
# - gawk
# - icarus-verilog
# - libxml++
# - qt5
before_install:
- source .travis/common.sh

2
.travis/common.sh
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@ -36,7 +36,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
# export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH"
# export PATH="/usr/local/opt/qt/bin:$PATH"
# Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h
sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target /
sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted
else
# For linux, we use g++-8 and gcc-8 as default compilers
export CC=gcc-8

2
.travis/script.sh
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@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2
python3 openfpga_flow/scripts/run_fpga_task.py single_mode blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3
end_section "OpenFPGA.TaskTun"

32
README.md
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@ -3,28 +3,32 @@
[![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
## Introduction
The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification testbenches/scripts. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.<br />
The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification [testbenches/scripts](./testbenches/scripts) OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
## Compilation
Dependencies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
Dependencies and help using docker can be found at [**./tutorials/building.md**](./tutorials/building.md).
**Compilation Steps:**
1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go inside it*
2. mkdir build && cd build # *Create a folder named build in the OpenPFGA repository*
3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create a Makefile in this folder using cmake*
4. make # *Compile the tool and its dependencies*
```bash
# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
mkdir build && cd build # Create a folder named build in the OpenPFGA repository
cmake .. -DCMAKE_BUILD_TYPE=debug # Create a Makefile in this folder using cmake
make # Compile the tool and its dependencies
```
*We currently implemented OpenFPGA for:*<br />
*1. Ubuntu 16.04*<br />
*2. Red Hat 7.5*<br />
*3. MacOS Mojave 10.14.4*<br /><br />
*Please note that those were the versions for which the tool was tested. It might work with earlier versions and other distributions.*
We currently target OpenFPGA for:
1. Ubuntu 16.04
2. Red Hat 7.5
3. MacOS Mojave 10.14.4
*The tool was tested with these operating systems. It might work with earlier versions and other distributions.*
## Documentation
OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.
## Tutorials
You can find some tutorials in the [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.
You can find some tutorials in the [**./tutorials**](./tutorials) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.
Through those tutorials, users can learn how to use the flow and install the different dependencies.<br />
The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through training and explain the folder oraganization as well as introducing some tips and commonly used keywords.
Through those tutorials, users can learn how to use the flow and install the different dependencies.
The [tutorial index](./tutorials/tutorial_index.md) will guide you through training and explain the folder oraganization as well as introducing some tips and commonly used keywords.

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2
docs/source/arch_lang/index.rst
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@ -8,6 +8,8 @@ Extended Architecture Description Language
:maxdepth: 2
generality
interconnect
spice_sim_setting

94
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@ -0,0 +1,94 @@
Interconnection extensions
==========================
This section introduces extensions on the architecture description file about existing interconnection description.
Directlist
----------
The original direct connections in the directlist section are documented here_. Its description is given below:
.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections
.. code-block:: xml
<directlist>
<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string"/>
</directlist>
.. note:: These options are required
Our extension include three more options:
.. code-block:: xml
<directlist>
<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string" interconnection_type="string" x_dir="string" y_dir="string"/>
</directlist>
.. note:: these options are optional. However, if *interconnection_type* is set *x_dir* and *y_dir* are required.
* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply.
* **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives:
* x_dir="positive":
* interconnection_type="column": a column will be connected to a column on the **right**, if it exists.
* interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists.
* x_dir="negative":
* interconnection_type="column": a column will be connected to a column on the **left**, if it exists.
* interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists.
* **y_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives:
* y_dir="positive":
* interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists.
* interconnection_type="row": a row will be connected on an **above** row, if it exists.
* y_dir="negative":
* interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists.
* interconnection_type="row": a row will be connected on a row **below**, if it exists.
Example
-------
For this example, we will study a scan-chain implementation. The description could be:
.. code-block:: xml
<directlist>
<direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0" interconnection_type="column" x_dir="positive" y_dir="positive"/>
</directlist>
:numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA.
.. _fig_p2p_exple:
.. figure:: ./figures/point2point_example.png
An example of scan-chain implementation
In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
Truth table
-----------
A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.
:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate.
.. _fig_p2p_trtable:
.. figure:: ./figures/point2point_truthtable.png
Point to point truth table

8
openfpga_flow/VerilogNetlists/ff.v
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@ -76,9 +76,9 @@ endmodule //End Of Module static_dff
//-----------------------------------------------------
module sc_dff_compact (
/* Global ports go first */
input reset, // Reset input
input pReset, // Reset input
//input set, // set input
input clk, // Clock Input
input prog_clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q, // Q output
@ -88,8 +88,8 @@ output Qb // Q output
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset /*or posedge set*/)
if (reset) begin
always @ ( posedge prog_clk or posedge pReset /*or posedge set*/)
if (pReset) begin
q_reg <= 1'b0;
//end else if (set) begin
// q_reg <= 1'b1;

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openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml Normal file
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@ -0,0 +1,631 @@
<!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
- General purpose logic block:
K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
with optionally registered outputs
Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
Carry chain links to vertically adjacent logic blocks
- Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.
Height = 6, found on every (8n+2)th column
- Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.
Height = 4, found on every (8n+6)th column
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
Details on Modelling:
The electrical design of the architecture described here is NOT from an
optimized, SPICED architecture. Instead, we attempt to create a reasonable
architecture file by using an existing commercial FPGA to approximate the area,
delay, and power of the underlying components. This is combined with a reasonable 40 nm
model of wiring and circuit design for low-level routing components, where available.
The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also
has wiring electrical parameters that allow the wire lengths and switch patterns to be
modified and you will still get reasonable delay results for the new architecture.
The following describes, in detail, how we obtained the various electrical values for this
architecture.
Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar
architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture.
(n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)
This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to
match the overall target (a 40 nm FPGA).
We obtain delay numbers by measuring delays of routing, soft logic blocks,
memories, and multipliers from test circuits on a Stratix IV GX device
(EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4
wires. Rmetal and Cmetal values for the routing wires were obtained from work done by Charles
Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and
take the R and C data from the ITRS roadmap.
For the general purpose logic block, we assume that the area and delays of the Stratix IV
crossbar is close enough to the crossbar modelled here. We use 40 inputs and 20 feedback lines in
the cluster and a full crossbar, leading to 53:1 multiplexers in front of each BLE input.
Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to
36:1 multiplexers. We require 60 such multiplexers, while Stratix IV requires 88 for its more
complex fracturable BLEs + the extra control signals. We justify this rough approximation as follows:
The Stratix IV crossbar has more inputs (72 vs. 60) and
outputs (88 vs. 60) than our full crossbar which should increase its area and delay, but the
Stratix IV crossbar is also 50% sparse (each mux is 36:1 instead of 53:1) which should reduce its
area and delay. The total number of crossbar switch points is roughly similar between the two
architectures (3160 for SIV and 3600 for the academic architecture below), so we use the area
& delay of the Stratix IV crossbar as a rough approximation of our crossbar.
For LUTs, we include LUT
delays measured from Stratix IV which is dependant on the input used (ie. some
LUT inputs are faster than others). The CAD tools at the time of VTR 7 does
not consider differences in LUT input delays.
Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.
Delay obtained by compiling a 256 bit adder (registered inputs and outputs,
all pins except clock virtual) then measuring the delays in chip-planner,
sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns,
inter-block carry delay = 0.327 ns. Given this data, I will approximate
sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and
inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has
overhead that we don't have, I'll approximate the delay of a simpler chain at
one half what they have. This is very rough, anything from 0.01ns to 0.327ns
can be justified).
Logic block area numbers obtained by scaling overall tile area of a 65nm
Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out
routing area at a channel width of 300. We use a channel width of 300 because it can route
all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
choosing a width that provides high routability. The architecture can be routed at different channel
widths, but we estimate the tile size and hence the physical length of routing wires assuming
a channel width of 300.
Sanity checks employed:
1. We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches
common electrical design.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0" tileable_routing="off"/>
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<!--clock op_freq="200e6" sim_slack="0.2" prog_freq="2.5e6"-->
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"> <!--frequency modified to speedup the fpga programing-->
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="${OPENFPGA_PATH}/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
<design_technology type="cmos" topology="OR"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="false">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="false">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV4X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="false">
<design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV4X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="unfrac_lut4" prefix="unfrac_lut4" dump_structural_verilog="false">
<design_technology type="cmos" fracturable_lut="false"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<lut_input_inverter exist="on" circuit_model_name="INV1X"/>
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-"/>
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="pReset" lib_name="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
<port type="input" prefix="D" lib_name="D" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
<port type="input" prefix="outpad" size="1"/>
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<!-- Hard logic definition for heterogenous blocks -->
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="input" prefix="cin" size="1"/>
<port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-->
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L16"/>
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
</segment>
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<!--switch_segment_patterns>
<pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
<unbuf_mux name="1"/>
<sb type ="pattern">0 1</sb>
</pattern>
</switch_segment_patterns-->
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io" capacity="2" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.§
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.30" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic
block. Note that the crossbar / local interconnect is considered part of the logic block
area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range.
-->
<pb_type name="clb" area="11388">
<input name="I" num_pins="12" equivalent="true"/>
<output name="O" num_pins="4" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
-->
<pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="logic" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<pb_type name="lut4" blif_model=".names" num_pb="1" circuit_model_name="unfrac_lut4" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
202e-12
202e-12
202e-12
202e-12
</delay_matrix>
</pb_type>
<interconnect>
<direct name="direct_lut_in" input="logic.in[3:0]" output="lut4.in[3:0]"/>
<direct name="direct_lut_out" input="lut4.out" output="logic.out"/>
</interconnect>
</pb_type>
<pb_type name="ff_phy" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
</pb_type>
<interconnect>
<complete name="direct_clk" input="fle.clk" output="ff_phy.clk"/>
<direct name="direct_in" input="fle.in[3:0]" output="logic.in[3:0]"/>
<direct name="direct_frac_out1" input="logic.out" output="ff_phy.D"/>
<mux name="mux_out" input="ff_phy.Q logic.out" output="fle.out">
</mux>
</interconnect>
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
delay within the crossbar is 95 ps.
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I" out_port="fle[3:0].in" />
<delay_constant max="70.2e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
</interconnect>
<fc default_in_type="frac" default_in_val="0.1" default_out_type="frac" default_out_val="0.10">
</fc>
<pinlocations pattern="custom">
<loc side="top">clb.clk </loc>
<loc side="right">clb.I[5:0] clb.O[1:0]</loc>
<loc side="bottom">clb.I[11:6] clb.O[3:2]</loc>
<loc side="left"></loc>
</pinlocations>
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
<power>
<local_interconnect C_wire="2.5e-10"/>
<mux_transistor_size mux_transistor_size="3"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="4"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="2.5e-10"/>
</clocks>
</architecture>

453
openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act Normal file
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@ -0,0 +1,453 @@
i_0_ 0.507200 0.496600
i_1_ 0.506400 0.501400
i_2_ 0.497600 0.493200
i_3_ 0.503800 0.496600
i_4_ 0.499400 0.493000
i_5_ 0.498600 0.493600
i_6_ 0.492000 0.500800
i_7_ 0.487800 0.500000
i_8_ 0.501800 0.499000
i_9_ 0.497000 0.485000
i_10_ 0.504400 0.496800
i_11_ 0.500000 0.509800
i_12_ 0.493800 0.498400
i_13_ 0.510600 0.493800
o_0_ 0.577000 0.077506
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n29 0.250000 0.047867
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n31 0.250000 0.092368
o_1_ 0.500400 0.069873
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n62 0.032000 0.002001
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n79 0.016800 0.000456
n80 0.181400 0.102631
n81 0.831000 0.000179
n82 0.239000 0.087621
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n112 0.117400 0.025304
n113 0.243000 0.090668
n114 0.954000 0.000523
n115 0.029600 0.001893
n116 0.046200 0.000537
n117 0.870200 0.013837
n118 0.972800 0.002734
n119 0.021600 0.168817
n120 0.693600 0.019730
n121 0.059000 0.007010
n122 0.894800 0.009692
n123 0.249800 0.090699
n124 0.230000 0.091866
n125 0.008200 0.000048
n126 0.028400 0.001814
n127 0.030000 0.001791
n128 0.249200 0.090461
n129 0.246400 0.089906
n130 0.005800 0.000000
n131 0.123800 0.026488
n132 0.844800 0.001778
n133 0.013600 0.000463
n134 0.975400 0.022212
n135 0.012000 0.000465
n136 0.032400 0.001740
n137 0.013400 0.000483
n138 0.010400 0.000524
n139 0.250600 0.096640
n140 0.253200 0.093930
n141 0.156000 0.027293
n142 0.013400 0.000451
n143 0.017600 0.000499
n144 0.009200 0.000005
n145 0.009200 0.222476
n146 0.012600 0.000443
n147 0.115600 0.026365
n148 0.682200 0.142413
n149 0.169400 0.000048
n150 0.660800 0.002077
n151 0.248800 0.094647
n152 0.278000 0.117457
n153 0.013200 0.000495
n154 0.130000 0.026721
n155 0.258000 0.093998
n156 0.775600 0.032205
n157 0.035400 0.056403
n158 0.121600 0.025516
n159 0.251800 0.096842
n160 0.057200 0.007075
n161 0.016000 0.000451
n162 0.021600 0.165889
n163 0.037000 0.000004
n164 0.849200 0.000008
n165 0.042000 0.076864
n166 0.075600 0.175072
n167 0.249400 0.093538
n168 0.255400 0.092782
n169 0.123600 0.026761
n170 0.017800 0.128969
n171 0.130800 0.025177
n172 0.886000 0.009532
n173 0.976600 0.017711
n174 0.895000 0.008650
n175 0.012400 0.001407
n176 0.246400 0.090668
n177 0.285600 0.012522
n178 0.395200 0.030715
n179 0.016200 0.000487
n180 0.859200 0.148776
n181 0.014200 0.000470
n182 0.259400 0.088136
n183 0.071000 0.007397
n184 0.696600 0.093048
n185 0.046200 0.002075
n186 0.920200 0.000007
n187 0.063000 0.057916
n188 0.028800 0.013875
n189 0.970600 0.000859
n190 0.937000 0.003505
n191 0.872000 0.091162
n192 0.066400 0.009362
n193 0.934400 0.010902
n194 0.641000 0.091467
n195 0.904800 0.028943
n196 0.783800 0.029159
n197 0.790000 0.055221
n198 0.840000 0.024270
n199 0.229800 0.033381
n200 0.906400 0.016808
n201 0.312000 0.002321
n202 0.852200 0.093593
n203 0.820400 0.145265
n204 0.903000 0.000927
n205 0.900600 0.009143
n206 0.921400 0.031099
n207 0.125000 0.025885
n208 0.105600 0.010699
n209 0.022600 0.005495
n210 0.969600 0.027547
n211 0.254800 0.093022
n212 0.345600 0.023938
n213 0.661000 0.004096
n214 0.016000 0.000289
n215 0.061600 0.008226
n216 0.251800 0.096233
n217 0.753800 0.016062
n218 0.727400 0.095865
n219 0.112600 0.184403
n220 0.022200 0.029346
n221 0.105400 0.000041
n222 0.190200 0.064251
n223 0.037800 0.002414
n224 0.851000 0.004439
n225 0.677600 0.003756
n226 0.023600 0.001085
n227 0.129600 0.029253
n228 0.012800 0.000019
n229 0.034000 0.036995
n230 0.129200 0.026492
n231 0.037000 0.000119
n232 0.009000 0.000226
n233 0.012600 0.009536
n234 0.922400 0.000458
n235 0.943400 0.086745
n236 0.049400 0.000454
n237 0.013600 0.000453
n238 0.030200 0.001828
n239 0.014200 0.004049
n240 0.498600 0.003736
n241 0.018800 0.010133
n242 0.020600 0.000541
n243 0.117400 0.027569
n244 0.125800 0.027392
n245 0.950000 0.001390
n246 0.017400 0.000497
n247 0.951600 0.001381
n248 0.002000 0.000016
n249 0.992400 0.026955
n250 0.126600 0.027428
n251 0.127600 0.029646
n252 0.015000 0.000487
n253 0.018000 0.000425
n254 0.006800 0.000118
n255 0.126200 0.025692
n256 0.005200 0.000029
n257 0.122600 0.026156
n258 0.001600 0.000002
n259 0.123400 0.027569
n260 0.053000 0.006742
n261 0.131000 0.026156
n262 0.129200 0.029253
n263 0.035000 0.000872
n264 0.051200 0.002442
n265 0.045400 0.003988
n266 0.246800 0.091866
n267 0.983200 0.000000
n268 0.016600 0.000233
n269 0.123400 0.028069
n270 0.064600 0.007073
n271 0.912000 0.006231
n272 0.012200 0.000162
n273 0.003200 0.000029
n274 0.925600 0.028384
n275 0.030800 0.002138
n276 0.121400 0.027550
n277 0.014400 0.000455
n278 0.251400 0.092392
n279 0.030800 0.001886
n280 0.992600 0.000044
n281 0.012400 0.000000
n282 0.017000 0.000517
n283 0.877400 0.059738
n284 0.121200 0.029253
n285 0.952800 0.001476
n286 0.003400 0.000721
n287 0.986200 0.027652
n288 0.065600 0.007314
n289 0.013400 0.000446
n290 0.934000 0.062027
n291 0.738200 0.147156
n292 0.992600 0.044684
n293 0.036200 0.002105
n294 0.031600 0.001876
n295 0.128200 0.026813
n296 0.013000 0.000487
n297 0.922800 0.002099
n298 0.610200 0.023513
n299 0.949200 0.028723
n300 0.984800 0.003947
n301 0.063000 0.007268
n302 0.957400 0.001338
n303 0.988000 0.004227
n304 0.063600 0.006975
n305 0.875600 0.010050
n306 0.008600 0.001044
n307 0.001800 0.004268
n308 0.985000 0.024177
n309 0.122000 0.026706
n310 0.061600 0.007346
n311 0.016200 0.000460
n312 0.127800 0.014131
n313 0.035800 0.002065
n314 0.001000 0.000017
n315 0.001200 0.000002
n316 0.001000 0.000001
n317 0.014000 0.000507
n318 0.003800 0.000029
n319 0.890400 0.009678
n320 0.962600 0.000001
n321 0.253600 0.090668
n322 0.030800 0.002077
n323 0.123400 0.027838
n324 0.133000 0.027838
n325 0.005400 0.000034
n326 0.002600 0.000009
n327 0.034400 0.001873
n328 0.992800 0.000057
n329 0.007200 0.000000
n330 0.006200 0.000050
n331 0.001800 0.000072
n332 0.001600 0.028311
n333 0.991600 0.049013
n334 0.994000 0.023346
n335 0.993200 0.000023
n336 0.990400 0.024989
n337 0.001400 0.000004
n338 0.014200 0.061698
n339 0.729000 0.037530
n340 0.910600 0.084521
n341 0.641200 0.013178
o_3_ 0.505400 0.099316
n343 0.328200 0.024360
n344 0.959800 0.003228
n345 0.373000 0.023259
n346 0.945800 0.000003
n347 0.051000 0.006230
n348 0.765800 0.137143
n349 0.033200 0.000847
n350 0.402000 0.011652
n351 0.436400 0.024182
n352 0.013400 0.007911
n353 0.222000 0.015781
n354 0.992200 0.000052
n355 0.936000 0.000087
n356 0.132600 0.085254
n357 0.145400 0.033973
n358 0.011000 0.000156
n359 0.063000 0.007116
n360 0.253000 0.015271
n361 0.294800 0.023465
n362 0.027200 0.006307
n363 0.312200 0.023937
n364 0.345800 0.017249
n365 0.833400 0.051311
n366 0.825400 0.034122
n367 0.223000 0.042498
n368 0.965200 0.001881
n369 0.014800 0.000445
n370 0.989000 0.239725
n371 0.120400 0.009204
n372 0.978800 0.000544
n373 0.652400 0.031285
n374 0.636400 0.152149
n375 0.931200 0.002467
n376 0.785200 0.137981
n377 0.415200 0.097289
n378 0.807600 0.030338
o_6_ 0.496800 0.138220
n380 0.516600 0.079201
n381 0.779000 0.000037
o_5_ 0.493000 0.128897
n383 0.155000 0.001954
n384 0.518600 0.039542
n385 0.624800 0.070955
n386 0.269400 0.164373
n387 0.143600 0.014543
n388 0.120200 0.098574
n389 0.941000 0.068389
n390 0.977600 0.088518
n391 0.861400 0.005270
n392 0.143600 0.026406
n393 0.811400 0.000941
n394 0.287400 0.057846
n395 0.985400 0.016065
o_7_ 0.133200 0.268048
n397 0.818400 0.000280
n398 0.973400 0.158761
n399 0.382000 0.045447
n400 0.949800 0.047076
n401 0.031400 0.002013
n402 0.018800 0.000245
n403 0.023800 0.000712
n404 0.930600 0.204221
n405 0.363400 0.040311
n406 0.009200 0.006631
n407 0.002800 0.000249
n408 0.073800 0.008696
n409 0.996400 0.000020
n410 0.010800 0.017350
n411 0.009600 0.007951
n412 0.008000 0.000017
n413 0.651200 0.036093
n414 0.984400 0.030970
n415 0.011800 0.000155
n416 0.581200 0.026865
n417 0.623000 0.027332
n418 0.016800 0.021673
n419 0.982600 0.000425
n420 0.957600 0.045049
n421 0.996600 0.002363
n422 0.991400 0.006621
n423 0.503000 0.090886
n424 0.002200 0.075540
n425 0.992000 0.166252
n426 0.982200 0.000305
n427 0.664600 0.000799
n428 0.700000 0.021303
o_2_ 0.583600 0.023724
n430 0.107200 0.003705
n431 0.946400 0.019926
n432 0.877600 0.000360
n433 0.987200 0.003971
n434 0.836800 0.005233
o_4_ 0.507000 0.223870
n436 0.046800 0.002377
n437 0.029000 0.112624
n438 0.963600 0.016971
n439 0.221000 0.068298
n440 0.097000 0.036002
n441 0.938400 0.000715
n442 0.909200 0.040030
n443 0.946000 0.001650
n444 0.833200 0.004141
n445 0.915400 0.000387
n446 0.577400 0.219264
n447 0.268200 0.172298
n448 0.280400 0.027999
n449 0.316800 0.052897
n450 0.926000 0.023917
n451 0.111200 0.011004
n452 0.071000 0.005452
n453 0.125400 0.077442
n454 0.182800 0.156557
n455 0.938000 0.000153
n456 0.078800 0.000481
n457 0.998000 0.000135
n458 0.938800 0.000000
n459 0.992000 0.000072
n460 0.998000 0.003630
n461 0.983800 0.120489
n462 0.998000 0.191415
n463 0.968000 0.000008

1360
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/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
module alu4(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_);
input i_0_;
input i_10_;
input i_11_;
input i_12_;
input i_13_;
input i_1_;
input i_2_;
input i_3_;
input i_4_;
input i_5_;
input i_6_;
input i_7_;
input i_8_;
input i_9_;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n147;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n163;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
wire n200;
wire n201;
wire n202;
wire n203;
wire n204;
wire n205;
wire n206;
wire n207;
wire n208;
wire n209;
wire n210;
wire n211;
wire n212;
wire n213;
wire n214;
wire n215;
wire n216;
wire n217;
wire n218;
wire n219;
wire n220;
wire n221;
wire n222;
wire n223;
wire n224;
wire n225;
wire n226;
wire n227;
wire n228;
wire n229;
wire n230;
wire n231;
wire n232;
wire n233;
wire n234;
wire n235;
wire n236;
wire n237;
wire n238;
wire n239;
wire n240;
wire n241;
wire n242;
wire n243;
wire n244;
wire n245;
wire n246;
wire n247;
wire n248;
wire n249;
wire n250;
wire n251;
wire n252;
wire n253;
wire n254;
wire n255;
wire n256;
wire n257;
wire n258;
wire n259;
wire n26;
wire n260;
wire n261;
wire n262;
wire n263;
wire n264;
wire n265;
wire n266;
wire n267;
wire n268;
wire n269;
wire n27;
wire n270;
wire n271;
wire n272;
wire n273;
wire n274;
wire n275;
wire n276;
wire n277;
wire n278;
wire n279;
wire n28;
wire n280;
wire n281;
wire n282;
wire n283;
wire n284;
wire n285;
wire n286;
wire n287;
wire n288;
wire n289;
wire n29;
wire n290;
wire n291;
wire n292;
wire n293;
wire n294;
wire n295;
wire n296;
wire n297;
wire n298;
wire n299;
wire n30;
wire n300;
wire n301;
wire n302;
wire n303;
wire n304;
wire n305;
wire n306;
wire n307;
wire n308;
wire n309;
wire n31;
wire n310;
wire n311;
wire n312;
wire n313;
wire n314;
wire n315;
wire n316;
wire n317;
wire n318;
wire n319;
wire n320;
wire n321;
wire n322;
wire n323;
wire n324;
wire n325;
wire n326;
wire n327;
wire n328;
wire n329;
wire n33;
wire n330;
wire n331;
wire n332;
wire n333;
wire n334;
wire n335;
wire n336;
wire n337;
wire n338;
wire n339;
wire n34;
wire n340;
wire n341;
wire n343;
wire n344;
wire n345;
wire n346;
wire n347;
wire n348;
wire n349;
wire n35;
wire n350;
wire n351;
wire n352;
wire n353;
wire n354;
wire n355;
wire n356;
wire n357;
wire n358;
wire n359;
wire n36;
wire n360;
wire n361;
wire n362;
wire n363;
wire n364;
wire n365;
wire n366;
wire n367;
wire n368;
wire n369;
wire n37;
wire n370;
wire n371;
wire n372;
wire n373;
wire n374;
wire n375;
wire n376;
wire n377;
wire n378;
wire n38;
wire n380;
wire n381;
wire n383;
wire n384;
wire n385;
wire n386;
wire n387;
wire n388;
wire n389;
wire n39;
wire n390;
wire n391;
wire n392;
wire n393;
wire n394;
wire n395;
wire n397;
wire n398;
wire n399;
wire n40;
wire n400;
wire n401;
wire n402;
wire n403;
wire n404;
wire n405;
wire n406;
wire n407;
wire n408;
wire n409;
wire n41;
wire n410;
wire n411;
wire n412;
wire n413;
wire n414;
wire n415;
wire n416;
wire n417;
wire n418;
wire n419;
wire n42;
wire n420;
wire n421;
wire n422;
wire n423;
wire n424;
wire n425;
wire n426;
wire n427;
wire n428;
wire n43;
wire n430;
wire n431;
wire n432;
wire n433;
wire n434;
wire n436;
wire n437;
wire n438;
wire n439;
wire n44;
wire n440;
wire n441;
wire n442;
wire n443;
wire n444;
wire n445;
wire n446;
wire n447;
wire n448;
wire n449;
wire n45;
wire n450;
wire n451;
wire n452;
wire n453;
wire n454;
wire n455;
wire n456;
wire n457;
wire n458;
wire n459;
wire n46;
wire n460;
wire n461;
wire n462;
wire n463;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
output o_0_;
output o_1_;
output o_2_;
output o_3_;
output o_4_;
output o_5_;
output o_6_;
output o_7_;
assign o_0_ = 64'hfffefffefffefefe >> { n30, n31, i_3_, n28, n29, n26 };
assign n34 = 4'h8 >> { i_8_, i_12_ };
assign n124 = 4'h2 >> { i_13_, i_12_ };
assign n125 = 8'ha8 >> { n127, n126, n49 };
assign n126 = 32'd128 >> { i_3_, i_13_, i_5_, i_4_, i_12_ };
assign n127 = 32'd8 >> { i_3_, i_5_, i_13_, i_4_, i_11_ };
assign n128 = 4'h8 >> { i_8_, i_7_ };
assign n129 = 4'h8 >> { i_9_, i_12_ };
assign n130 = 64'h0800080008080800 >> { n132, n131, n133, i_5_, i_6_, i_8_ };
assign n131 = 8'h02 >> { i_9_, i_13_, i_11_ };
assign n132 = 32'd4025479150 >> { i_3_, i_12_, i_4_, i_2_, i_0_ };
assign n133 = 64'h0000000000008000 >> { i_0_, i_11_, i_2_, i_3_, i_12_, i_9_ };
assign n35 = 4'h2 >> { i_8_, i_11_ };
assign n134 = 64'h0015151515151515 >> { i_9_, n42, n91, n67, n136, n135 };
assign n135 = 64'h0000000000000080 >> { i_10_, i_9_, i_13_, i_5_, i_4_, i_12_ };
assign n136 = 32'd8 >> { i_10_, i_13_, i_12_, i_7_, i_11_ };
assign n137 = 64'h0000000000000080 >> { i_8_, i_0_, i_12_, i_2_, i_1_, i_11_ };
assign n138 = 64'h0000008000080088 >> { i_11_, i_12_, i_3_, i_8_, n99, n139 };
assign n139 = 4'h1 >> { i_9_, i_13_ };
assign n140 = 4'h8 >> { i_9_, i_1_ };
assign n141 = 32'd2290122880 >> { i_8_, i_3_, i_7_, i_2_, i_0_ };
assign n142 = 64'h0000000000000002 >> { i_2_, i_1_, i_0_, i_13_, i_11_, i_12_ };
assign n143 = 64'h0000000000000080 >> { i_0_, i_4_, i_12_, i_1_, i_3_, i_11_ };
assign n36 = 4'h1 >> { i_6_, i_5_ };
assign n144 = 32'd269488400 >> { i_9_, n87, n142, i_8_, i_3_ };
assign n145 = 32'd2290657416 >> { i_0_, i_2_, n88, n146, n101 };
assign n146 = 64'h0000000000000008 >> { i_3_, i_10_, i_0_, i_13_, i_4_, i_12_ };
assign n147 = 8'h02 >> { i_10_, i_13_, i_12_ };
assign n148 = 8'h15 >> { i_12_, n71, n99 };
assign n149 = 64'h4544454455554544 >> { n156, n154, n155, n150, n152, i_0_ };
assign n150 = 32'd1162151237 >> { i_8_, i_3_, n151, i_7_, n56 };
assign n151 = 4'h8 >> { i_2_, i_1_ };
assign n152 = 64'he4e4e4e4e4e4e4e6 >> { i_11_, i_6_, i_1_, n153, i_13_, i_12_ };
assign n153 = 64'h0000000000000001 >> { i_10_, i_6_, i_7_, i_2_, i_13_, i_11_ };
assign n37 = 16'hdd0d >> { i_5_, i_1_, i_6_, i_0_ };
assign n154 = 8'h01 >> { i_8_, i_6_, i_7_ };
assign n155 = 4'h2 >> { i_12_, i_10_ };
assign n156 = 64'hbfff9dddafafafad >> { i_4_, i_13_, i_3_, i_11_, i_10_, i_12_ };
assign n157 = 32'd134785544 >> { i_1_, i_6_, i_2_, n54, n108 };
assign n158 = 8'h80 >> { i_8_, i_6_, i_7_ };
assign n159 = 4'h8 >> { i_3_, i_1_ };
assign n160 = 16'h0008 >> { i_9_, i_13_, i_4_, i_11_ };
assign n161 = 64'h0000000000000002 >> { i_2_, i_1_, i_0_, i_13_, i_12_, i_11_ };
assign n162 = 32'd2829626024 >> { n61, n60, n59, n62, n113 };
assign n163 = 32'd1145328708 >> { i_9_, n108, n50, n160, i_10_ };
assign n38 = 64'h4555055544550455 >> { i_7_, n37, i_3_, i_2_, n39, i_12_ };
assign n164 = 64'h0002000000020002 >> { n93, n90, n170, n165, n166, n173 };
assign n165 = 32'd134776840 >> { i_8_, i_3_, i_7_, i_10_, n42 };
assign n166 = 32'd2155915904 >> { i_6_, n168, n167, n169, i_1_ };
assign n167 = 4'h8 >> { i_3_, i_2_ };
assign n168 = 4'h2 >> { i_11_, i_10_ };
assign n169 = 8'h02 >> { i_8_, i_11_, i_10_ };
assign n170 = 32'd1426326532 >> { n171, i_8_, i_10_, n33, n172 };
assign n171 = 8'h01 >> { i_10_, i_13_, i_12_ };
assign n172 = 64'hfffdfffdfffddddd >> { i_7_, i_1_, i_6_, i_2_, i_3_, i_0_ };
assign n173 = 64'h0ddddddddddddddd >> { n92, i_6_, i_2_, i_12_, n174, n160 };
assign n39 = 4'h1 >> { n36, n40 };
assign n174 = 64'hffefffefeeeeffef >> { i_1_, i_8_, i_3_, i_6_, i_2_, i_0_ };
assign n175 = 64'h0000000800080008 >> { i_12_, i_8_, i_3_, i_6_, n73, n176 };
assign n176 = 4'h1 >> { i_13_, i_11_ };
assign n177 = 64'h0001000100010000 >> { i_4_, n180, n179, n153, i_5_, n178 };
assign n178 = 64'haa20aa24aa21aa25 >> { i_11_, i_12_, i_13_, i_1_, i_6_, i_10_ };
assign n179 = 64'h0000000000000002 >> { i_10_, i_8_, i_6_, i_7_, i_13_, i_4_ };
assign n180 = 64'h7f7f7f7f7f7f7f77 >> { i_7_, i_8_, i_6_, i_12_, i_10_, i_11_ };
assign n181 = 64'h0000000000000008 >> { i_8_, i_9_, i_13_, i_11_, i_6_, i_7_ };
assign n182 = 4'h1 >> { i_13_, i_12_ };
assign n183 = 64'h8080008000800080 >> { i_8_, i_3_, i_4_, i_9_, i_12_, i_11_ };
assign n40 = 32'd1079002196 >> { i_5_, i_6_, i_0_, i_1_, i_7_ };
assign n184 = 32'd2012686247 >> { i_13_, i_3_, i_4_, i_12_, i_9_ };
assign n185 = 64'h8000800080000000 >> { i_11_, i_6_, i_7_, i_2_, i_12_, i_9_ };
assign n186 = 32'd1431655764 >> { i_2_, i_13_, n65, i_9_, n187 };
assign n187 = 8'h02 >> { i_10_, i_9_, n33 };
assign n188 = 32'd1360072977 >> { i_5_, n111, i_6_, n189, i_1_ };
assign n189 = 64'hfffffffd7fff7ffd >> { i_9_, i_10_, i_8_, i_7_, i_5_, n33 };
assign n190 = 64'hfffffffeff7fff7e >> { i_9_, i_10_, i_13_, i_7_, i_5_, i_6_ };
assign n191 = 32'd2004309879 >> { i_11_, n67, n182, i_10_, n140 };
assign n192 = 32'd1 >> { n34, n35, i_10_, i_9_, i_13_ };
assign n193 = 64'h7ff7fff77fffffff >> { i_11_, i_12_, i_6_, i_7_, i_10_, i_9_ };
assign n41 = 32'd2863311522 >> { i_3_, n34, n35, n27, n42 };
assign n194 = 64'h8088828a828a828a >> { i_3_, n31, n70, i_13_, i_11_, n195 };
assign n195 = 32'd2004317959 >> { i_4_, i_11_, n34, n108, n50 };
assign n196 = 64'heeffeef5e6f7e6f5 >> { i_10_, i_3_, i_11_, i_13_, i_4_, i_12_ };
assign n197 = 64'hffef0000ffe70000 >> { i_13_, n198, i_2_, i_3_, i_4_, i_11_ };
assign n198 = 64'hffbfffbfdd9dffbf >> { n70, i_3_, n31, n33, i_11_, i_10_ };
assign n199 = 64'hfd00fd00fd00ff00 >> { i_7_, n200, i_2_, n201, n187, n202 };
assign n200 = 64'heeeeeeefeefeeeff >> { n182, n176, n33, i_8_, i_10_, i_3_ };
assign n201 = 32'd286331152 >> { i_13_, n35, n34, n33, n27 };
assign n202 = 64'h7f7f7f7f7f7f7f7e >> { i_13_, i_12_, i_11_, i_3_, i_10_, i_9_ };
assign n203 = 64'h0080a2a200a2a2a2 >> { n53, n124, n70, n204, i_2_, n205 };
assign n42 = 8'h80 >> { i_2_, i_1_, i_0_ };
assign n204 = 64'hddffdddfddfddddd >> { i_11_, i_12_, i_4_, i_8_, i_3_, n139 };
assign n205 = 64'hfffdfffd7f7dfffd >> { i_13_, i_8_, i_12_, i_2_, i_4_, i_3_ };
assign n206 = 32'd2004289399 >> { i_12_, i_3_, n207, n105, n26 };
assign n207 = 8'h80 >> { i_8_, i_9_, i_7_ };
assign n208 = 16'h5515 >> { n77, n78, n81, i_13_ };
assign n209 = 32'd526344 >> { i_12_, i_8_, i_6_, n73, n176 };
assign n210 = 8'h15 >> { n111, n158, n181 };
assign n211 = 4'h8 >> { i_10_, i_9_ };
assign n212 = 64'hfa50fa50c800c040 >> { i_13_, i_7_, i_9_, i_10_, i_2_, i_6_ };
assign n213 = 32'd33685506 >> { n217, n216, n214, n215, n218 };
assign n43 = 32'd1467441023 >> { i_1_, i_0_, i_6_, i_5_, i_2_ };
assign n214 = 64'h0800080008000808 >> { i_3_, i_11_, i_4_, i_8_, n73, n124 };
assign n215 = 8'h08 >> { i_7_, n155, i_2_ };
assign n216 = 4'h2 >> { i_12_, i_11_ };
assign n217 = 64'hfdd0fdddffd0ffdd >> { i_10_, i_2_, i_4_, i_8_, i_7_, i_3_ };
assign n218 = 32'd3149642681 >> { i_7_, i_2_, i_11_, i_13_, i_12_ };
assign n219 = 4'h2 >> { i_11_, n124 };
assign n220 = 64'haa08aa00aa08aa08 >> { i_2_, n73, n74, i_1_, n53, n124 };
assign n221 = 64'h5454545455545454 >> { i_4_, n227, n216, n226, n222, i_1_ };
assign n222 = 32'd1157973317 >> { n224, n223, n225, i_7_, i_6_ };
assign n223 = 32'd2155905160 >> { i_3_, i_12_, i_4_, n131, i_8_ };
assign n26 = 4'h2 >> { n27, i_2_ };
assign n44 = 32'd1465341951 >> { i_5_, i_0_, i_6_, i_1_, i_7_ };
assign n224 = 64'h7077f0ff70777077 >> { i_4_, n31, n108, i_2_, n96, i_3_ };
assign n225 = 32'd3104422667 >> { n53, n90, i_2_, i_13_, i_11_ };
assign n226 = 32'd134744064 >> { i_2_, i_7_, i_11_, n103, n34 };
assign n227 = 8'h02 >> { i_8_, i_7_, i_6_ };
assign n228 = 64'h0200020002020200 >> { i_3_, n108, n160, i_2_, i_1_, i_8_ };
assign n229 = 64'h2200222022202220 >> { i_2_, i_7_, n230, n35, i_10_, n33 };
assign n230 = 8'h02 >> { i_3_, i_2_, i_1_ };
assign n231 = 64'h0800080008080800 >> { i_4_, i_11_, i_3_, i_8_, n151, i_10_ };
assign n232 = 64'h8000800080008808 >> { i_3_, i_11_, i_4_, i_8_, n54, n124 };
assign n233 = 32'd572662434 >> { i_8_, i_6_, n110, n234, n230 };
assign n45 = 64'hff3f5f0f77335501 >> { i_6_, i_7_, i_5_, i_1_, i_2_, i_0_ };
assign n234 = 64'hfdfffdfffdfdfdff >> { i_12_, i_8_, i_4_, i_13_, i_9_, i_6_ };
assign n235 = 64'h1555555555555555 >> { i_3_, i_7_, i_12_, n56, n30, n236 };
assign n236 = 64'h0008000000080008 >> { i_7_, i_9_, i_6_, i_11_, i_2_, i_10_ };
assign n237 = 64'h0000000000000080 >> { i_10_, i_9_, i_13_, i_6_, i_4_, i_12_ };
assign n238 = 64'h8880080008000800 >> { n105, i_1_, i_2_, i_12_, i_9_, n82 };
assign n239 = 16'h0080 >> { i_6_, i_7_, n34, n168 };
assign n240 = 32'd1431393360 >> { i_11_, i_12_, i_1_, i_6_, n28 };
assign n241 = 64'h2000200022222000 >> { i_2_, n70, n27, n53, i_1_, n124 };
assign n242 = 32'd2861206154 >> { n243, n49, n245, n54, n244 };
assign n243 = 8'h08 >> { i_8_, i_6_, i_7_ };
assign n46 = 64'h8888880080808000 >> { i_6_, i_0_, i_5_, i_1_, i_3_, i_7_ };
assign n244 = 8'h80 >> { i_3_, i_5_, i_4_ };
assign n245 = 64'hfffffffffffffbd7 >> { i_8_, i_0_, i_6_, i_7_, i_2_, i_1_ };
assign n246 = 64'h0000000080000000 >> { i_9_, i_3_, i_7_, i_1_, i_0_, i_4_ };
assign n247 = 64'hfffffffffdfff77f >> { i_8_, i_2_, i_6_, i_1_, i_7_, i_0_ };
assign n248 = 64'h2222222222222202 >> { n258, n254, n256, n249, i_5_, n105 };
assign n249 = 64'h00110fff01110fff >> { n171, n251, n250, n252, n161, n253 };
assign n250 = 8'h08 >> { i_2_, i_1_, i_0_ };
assign n251 = 8'h08 >> { i_6_, i_8_, i_7_ };
assign n252 = 64'h0000000000000002 >> { i_10_, i_6_, i_7_, i_13_, i_11_, i_8_ };
assign n253 = 64'h0000000000000008 >> { i_10_, i_1_, i_13_, i_11_, i_2_, i_0_ };
assign n47 = 64'h777f7f7f77ff7fff >> { i_1_, i_0_, i_6_, i_5_, i_3_, i_2_ };
assign n254 = 16'ha888 >> { n171, n255, n107, n158 };
assign n255 = 8'h08 >> { i_1_, i_2_, i_0_ };
assign n256 = 32'd2290122880 >> { i_10_, i_6_, n158, n108, n257 };
assign n257 = 8'h02 >> { i_1_, i_0_, i_2_ };
assign n258 = 8'h80 >> { n99, n87, n259 };
assign n259 = 8'h08 >> { i_7_, i_6_, i_8_ };
assign n260 = 16'h0008 >> { i_13_, i_11_, i_12_, i_10_ };
assign n261 = 8'h02 >> { i_2_, i_0_, i_1_ };
assign n262 = 8'h02 >> { i_6_, i_7_, i_8_ };
assign n263 = 64'haaa8a8a8a8a8a8a8 >> { i_8_, i_5_, n82, n265, n264, n266 };
assign n48 = 4'h1 >> { i_3_, i_2_ };
assign n264 = 64'h8888800080008000 >> { i_1_, i_5_, i_6_, i_0_, i_10_, n167 };
assign n265 = 32'd134742024 >> { i_5_, i_0_, i_11_, i_6_, n48 };
assign n266 = 4'h2 >> { i_12_, i_13_ };
assign n267 = 64'h5555555515555555 >> { i_2_, n270, n36, n128, n105, n268 };
assign n268 = 64'h0000008000080088 >> { i_11_, i_12_, i_4_, i_5_, n269, i_10_ };
assign n269 = 8'h80 >> { i_3_, i_2_, i_1_ };
assign n270 = 16'h0002 >> { i_10_, i_13_, i_12_, i_11_ };
assign n271 = 64'h0002020202020202 >> { i_6_, n279, n278, n272, n273, n274 };
assign n272 = 64'h0000080000000880 >> { i_13_, i_5_, i_10_, i_4_, n154, i_3_ };
assign n273 = 8'h80 >> { n158, n139, n244 };
assign n49 = 8'h01 >> { i_2_, i_1_, i_0_ };
assign n274 = 64'h0000777077707770 >> { n275, n276, n202, i_4_, n243, n277 };
assign n275 = 32'd128 >> { i_7_, i_12_, i_10_, i_13_, i_8_ };
assign n276 = 8'h01 >> { i_3_, i_6_, i_5_ };
assign n277 = 64'h0000000000000080 >> { i_3_, i_9_, i_13_, i_5_, i_4_, i_11_ };
assign n278 = 4'h2 >> { i_3_, i_5_ };
assign n279 = 32'd128 >> { i_8_, i_11_, i_7_, i_13_, i_9_ };
assign n280 = 32'd4278189309 >> { n210, n209, i_3_, i_4_, i_5_ };
assign n281 = 64'h2020202020202022 >> { i_13_, n283, i_10_, n282, i_9_, i_4_ };
assign n282 = 64'h8000800080808000 >> { i_10_, i_1_, i_6_, n128, n124, i_5_ };
assign n283 = 32'd125269879 >> { i_2_, i_0_, n159, n40, n35 };
assign n50 = 4'h2 >> { i_3_, i_8_ };
assign n284 = 8'h02 >> { i_8_, i_6_, i_7_ };
assign n285 = 64'hfff7ffffffff7ff7 >> { i_6_, i_1_, i_7_, i_2_, i_8_, i_0_ };
assign n286 = 64'h0082000200800000 >> { n108, n131, i_5_, i_3_, i_4_, n262 };
assign n287 = 64'h0000077707770777 >> { n288, n276, n243, n289, n154, n127 };
assign n288 = 16'h0002 >> { i_8_, i_7_, i_11_, i_13_ };
assign n289 = 64'h0000000000000008 >> { i_3_, i_13_, i_4_, i_11_, i_12_, i_5_ };
assign n290 = 64'h0ddddddddddddddd >> { n129, n91, n259, n176, n291, n266 };
assign n291 = 64'haeeeeeeeeeeeeeee >> { i_7_, i_5_, i_8_, i_6_, i_11_, i_3_ };
assign n292 = 32'd2105540095 >> { n294, n293, i_6_, i_5_, i_3_ };
assign n293 = 32'd128 >> { i_7_, i_11_, i_8_, i_13_, i_9_ };
assign n51 = 32'd1381653 >> { i_5_, i_0_, i_6_, i_1_, i_3_ };
assign n294 = 32'd128 >> { i_8_, i_12_, i_7_, i_13_, i_10_ };
assign n295 = 8'h08 >> { i_11_, i_9_, i_8_ };
assign n296 = 64'h0000000000000002 >> { i_3_, i_6_, i_2_, i_5_, i_11_, i_10_ };
assign n297 = 32'd2004289399 >> { n298, n31, i_10_, n92, n51 };
assign n298 = 64'h015533770f5f3fff >> { i_6_, i_7_, i_5_, i_1_, i_2_, i_0_ };
assign n299 = 64'hddcdefcdffefefef >> { n295, i_6_, i_1_, n169, i_2_, i_5_ };
assign n300 = 64'h0000dd0ddd0ddd0d >> { n262, n270, n302, n301, n247, n87 };
assign n301 = 16'h0002 >> { i_9_, i_13_, i_12_, i_11_ };
assign n302 = 64'hffffffff7dffff7f >> { i_0_, i_6_, i_1_, i_2_, i_7_, i_8_ };
assign n303 = 64'h0000dd0ddd0ddd0d >> { n181, i_12_, n285, n301, n245, n87 };
assign n52 = 32'd1162149957 >> { i_5_, i_0_, i_1_, i_6_, i_3_ };
assign n304 = 16'h0002 >> { i_10_, i_9_, i_13_, i_11_ };
assign n305 = 64'hdddfdfdfddffdfff >> { i_1_, i_3_, i_6_, i_8_, i_9_, i_7_ };
assign n306 = 32'd8 >> { i_10_, i_7_, i_13_, n36, n35 };
assign n307 = 64'haaaaaaaaaaaaaaa2 >> { n316, n318, n314, n315, n308, n257 };
assign n308 = 64'h0000077707770777 >> { n312, n310, n311, n284, n309, n313 };
assign n309 = 8'h80 >> { i_3_, i_6_, i_5_ };
assign n310 = 16'h0080 >> { i_11_, i_7_, i_13_, i_9_ };
assign n311 = 64'h0000000000000008 >> { i_3_, i_9_, i_5_, i_13_, i_4_, i_11_ };
assign n312 = 16'h0009 >> { i_6_, i_5_, i_3_, i_8_ };
assign n313 = 32'd8 >> { i_8_, i_7_, i_12_, i_13_, i_10_ };
assign n53 = 4'h2 >> { i_3_, i_4_ };
assign n314 = 32'd32768 >> { i_5_, n105, n113, n227, n155 };
assign n315 = 16'h8000 >> { n176, n91, n129, n251 };
assign n316 = 4'h8 >> { n260, n317 };
assign n317 = 64'h0000000000000008 >> { i_8_, i_6_, i_7_, i_4_, i_5_, i_3_ };
assign n318 = 8'h80 >> { n278, n275, i_6_ };
assign n319 = 64'hffdfffdfddddffdf >> { i_7_, i_1_, i_6_, i_2_, i_4_, i_0_ };
assign n320 = 32'd1431639381 >> { i_7_, n36, n321, n30, n322 };
assign n321 = 4'h2 >> { i_11_, i_13_ };
assign n322 = 32'd128 >> { i_12_, i_11_, i_13_, i_10_, i_9_ };
assign n323 = 8'h02 >> { i_3_, i_5_, i_6_ };
assign n27 = 8'h1b >> { i_9_, i_10_, i_7_ };
assign n54 = 8'h08 >> { i_9_, i_6_, i_7_ };
assign n324 = 8'h02 >> { i_3_, i_6_, i_5_ };
assign n325 = 16'h8000 >> { n128, n266, n324, i_10_ };
assign n326 = 4'h8 >> { n227, n311 };
assign n327 = 32'd8 >> { i_9_, i_13_, i_4_, i_3_, i_5_ };
assign n328 = 64'hffff7fff7fffffff >> { i_3_, i_8_, n36, i_10_, n266, i_7_ };
assign n329 = 32'd1414813012 >> { n58, n112, n331, n330, i_5_ };
assign n330 = 64'h0080008088880080 >> { i_8_, n151, i_6_, n167, n304, i_4_ };
assign n331 = 32'd128 >> { i_7_, i_11_, n269, n30, n103 };
assign n332 = 16'h2aaa >> { n333, n334, n335, n93 };
assign n333 = 64'he7f7efffefffefff >> { n207, n321, n275, i_5_, i_6_, i_3_ };
assign n55 = 4'h2 >> { n56, i_5_ };
assign n334 = 16'h0777 >> { n279, n323, n243, n311 };
assign n335 = 64'h7777777707777777 >> { i_6_, i_3_, n313, i_5_, n155, n317 };
assign n336 = 64'h0000077707770777 >> { n323, n275, n279, n324, n284, n277 };
assign n337 = 32'd2860548224 >> { n155, n227, n101, n169, n327 };
assign n338 = 64'h8000800080008888 >> { n45, i_8_, n36, n167, n321, n211 };
assign n339 = 64'h5f4c0f0c5d4c0d0c >> { i_7_, n37, n45, n26, i_8_, n36 };
assign n340 = 64'h0222022213330222 >> { n62, n58, n71, n70, n84, i_5_ };
assign n341 = 64'h0000000000000080 >> { n68, n72, n80, n63, n75, n69 };
assign o_3_ = 16'h7fff >> { n340, n344, n341, o_2_ };
assign n343 = 64'h5707130355051101 >> { i_8_, i_6_, i_7_, i_2_, i_1_, i_3_ };
assign n56 = 4'h2 >> { i_6_, i_1_ };
assign n344 = 16'hff7f >> { i_9_, n343, i_5_, i_4_ };
assign n345 = 64'h2030253522322737 >> { i_2_, i_10_, i_3_, i_7_, i_9_, i_8_ };
assign n346 = 32'd1431655701 >> { i_1_, i_0_, i_4_, n345, n79 };
assign n347 = 64'ha2a2eea2a0a0eca0 >> { n49, n148, n139, n85, i_8_, n147 };
assign n348 = 64'h55005d085d085d08 >> { i_4_, n347, n164, n149, n444, i_5_ };
assign n349 = 64'hfaaaf888f888f888 >> { i_10_, n42, n109, n108, n107, n105 };
assign n350 = 64'h5555454d5555004c >> { i_1_, i_5_, i_6_, i_4_, i_3_, i_8_ };
assign n351 = 64'h0f008f881f119f99 >> { i_11_, i_12_, i_4_, i_3_, i_5_, i_7_ };
assign n352 = 64'h0000000800800088 >> { i_9_, i_10_, i_13_, i_5_, n351, n99 };
assign n353 = 64'h0081008188891191 >> { i_2_, i_6_, i_1_, i_7_, i_8_, i_5_ };
assign n57 = 8'h01 >> { i_9_, i_7_, i_11_ };
assign n354 = 64'hff77fff7ff7fffff >> { n110, n111, i_3_, i_8_, i_0_, n353 };
assign n355 = 64'h0808080808088808 >> { n76, n84, n346, n112, n114, n354 };
assign n356 = 64'h4602020244000002 >> { i_4_, i_3_, i_11_, i_13_, i_10_, i_12_ };
assign n357 = 64'h80aa008080800080 >> { i_6_, i_3_, i_4_, i_1_, i_8_, i_5_ };
assign n358 = 16'h8000 >> { n357, i_7_, i_0_, n129 };
assign n359 = 16'h0008 >> { i_3_, i_13_, i_0_, i_4_ };
assign n360 = 64'h058045c405004544 >> { i_11_, i_1_, i_6_, i_2_, i_7_, i_9_ };
assign n361 = 64'he8a8c888e0a0c000 >> { i_8_, i_7_, i_6_, i_3_, i_2_, i_1_ };
assign n362 = 64'h5444444444444444 >> { i_9_, i_0_, i_12_, n361, n137, i_4_ };
assign n363 = 64'hd8d85058c8884008 >> { i_2_, i_4_, i_3_, i_12_, i_8_, i_11_ };
assign n58 = 8'h51 >> { n61, n60, n59 };
assign n364 = 64'h9999b9999888a888 >> { n140, i_9_, i_7_, n363, i_13_, i_11_ };
assign n365 = 32'd2867571439 >> { i_6_, n157, i_13_, n364, i_0_ };
assign n366 = 64'hdf7fdf7f5777df7f >> { i_6_, i_3_, i_8_, i_1_, i_0_, i_2_ };
assign n367 = 64'h55d5f5f54480f5f5 >> { n158, n366, i_7_, i_10_, n159, i_0_ };
assign n368 = 32'd4286447487 >> { i_12_, i_4_, i_0_, i_11_, n367 };
assign n369 = 64'h0000000000000008 >> { i_3_, i_9_, i_0_, i_13_, i_4_, i_11_ };
assign n370 = 32'd926381879 >> { i_6_, i_1_, n369, i_7_, n161 };
assign n371 = 64'h2050205022722050 >> { i_11_, n182, i_8_, n33, i_9_, i_6_ };
assign n372 = 32'd4286578557 >> { i_10_, i_2_, i_6_, i_5_, n371 };
assign n373 = 32'd1434408318 >> { i_11_, i_13_, i_1_, i_6_, i_9_ };
assign n59 = 32'd2 >> { i_10_, i_8_, i_7_, i_1_, i_4_ };
assign n374 = 32'd2863311522 >> { i_2_, i_13_, i_12_, n54, n373 };
assign n375 = 32'd1997010695 >> { i_2_, n190, n53, n129, n94 };
assign n376 = 32'd2147518472 >> { n192, n193, i_3_, n375, n191 };
assign n377 = 64'hfa52aa02fa72aa22 >> { n30, n33, i_12_, i_3_, i_13_, i_7_ };
assign n378 = 64'hfbddeaccf9dde8cc >> { n196, n194, n377, i_8_, i_2_, i_7_ };
assign o_6_ = 64'hff77fff7ff7fffff >> { n197, n203, n199, i_7_, n378, n206 };
assign n380 = 64'h92b293b312321333 >> { i_9_, n219, n155, i_3_, i_8_, i_2_ };
assign n381 = 64'h1150554011105540 >> { i_12_, n380, i_1_, n213, i_8_, n220 };
assign o_5_ = 64'hfff5fffdfff7ffff >> { n391, n381, n386, n221, i_6_, n393 };
assign n383 = 32'd538976290 >> { i_7_, i_8_, i_12_, i_4_, i_11_ };
assign n60 = 8'h02 >> { i_10_, i_2_, i_4_ };
assign n384 = 64'h6e6e6e6e446e6e6e >> { n53, i_12_, n207, i_9_, n383, i_6_ };
assign n385 = 16'h2131 >> { i_10_, n384, n212, i_6_ };
assign n386 = 32'd2863311402 >> { n208, n388, n385, n186, i_1_ };
assign n387 = 64'he444e040e040e040 >> { i_6_, n31, i_12_, n211, i_11_, i_7_ };
assign n388 = 32'd3722304909 >> { n192, n209, n210, n387, i_3_ };
assign n389 = 64'h1113131313131313 >> { i_12_, i_7_, i_3_, n167, n231, n169 };
assign n390 = 64'h9dddbfffbfffbfff >> { n94, n105, n53, n131, i_7_, i_1_ };
assign n391 = 32'd8 >> { n163, n228, n229, n390, n389 };
assign n392 = 64'hffaeaeaeaeaeaeae >> { n34, i_2_, n28, n240, n167, n239 };
assign n393 = 64'h0008000800000008 >> { i_4_, n392, n232, n233, n450, n235 };
assign n61 = 16'heac8 >> { i_1_, i_8_, i_3_, i_6_ };
assign n394 = 64'hff81ff01ff80ff00 >> { n30, n31, n211, i_5_, i_7_, i_6_ };
assign n395 = 64'h55d5d5d5d5d5d5d5 >> { i_13_, i_3_, n394, n280, n271, n42 };
assign o_7_ = 64'hffffffff7fffffff >> { n403, n398, n395, n455, n458, n463 };
assign n397 = 64'h2222222202222222 >> { i_9_, i_4_, i_5_, n343, n72, n69 };
assign n398 = 32'd232588629 >> { n75, n452, n147, n397, n112 };
assign n399 = 64'ha8cca0cc88cc80cc >> { i_8_, i_6_, i_5_, i_1_, i_3_, i_2_ };
assign n400 = 64'h00ff007f00f70077 >> { n247, i_9_, n246, i_5_, n399, i_4_ };
assign n401 = 32'd2726330496 >> { n87, n261, n42, i_6_, i_8_ };
assign n402 = 64'hf970b920d9509900 >> { n49, n257, n401, n260, i_7_, i_6_ };
assign n403 = 64'hff00fd00fd00fd00 >> { n91, n402, i_9_, n248, n263, n267 };
assign n62 = 32'd2 >> { i_10_, i_8_, i_6_, i_7_, i_4_ };
assign n404 = 64'h7f7f7f7f557f7f7f >> { i_11_, i_7_, n52, n46, i_10_, i_9_ };
assign n405 = 64'h64ec74fc44cc54dc >> { n73, i_2_, n285, i_1_, i_5_, i_4_ };
assign n406 = 64'h88a8002000200020 >> { n99, n284, i_0_, n243, i_5_, n155 };
assign n407 = 32'd2155905024 >> { i_4_, n406, i_3_, n405, n131 };
assign n408 = 64'h0042004000400040 >> { i_10_, i_11_, i_13_, i_4_, i_12_, i_3_ };
assign n409 = 64'hfffffff77fffffff >> { i_3_, i_8_, i_6_, i_5_, i_7_, n408 };
assign n410 = 64'haaaaaaaa2aaaaaaa >> { n286, n409, n287, n290, n292, n49 };
assign n411 = 64'h2202020202020202 >> { i_7_, i_1_, i_0_, n43, i_9_, n87 };
assign n412 = 64'h0500454415115555 >> { n300, n303, n411, i_8_, i_5_, i_4_ };
assign n413 = 64'hae2eae2eff7fae2e >> { i_7_, i_3_, i_9_, i_8_, i_2_, i_6_ };
assign n63 = 16'h1011 >> { n67, n65, n66, n64 };
assign n414 = 64'hdd7f5d5fff7f5f5f >> { n304, n305, n413, n147, i_6_, i_0_ };
assign n415 = 8'ha2 >> { n306, n414, i_4_ };
assign n416 = 64'h7745774577557745 >> { i_1_, i_6_, i_4_, i_2_, i_5_, i_3_ };
assign n417 = 64'h5d5d5d5d595d5d5d >> { i_9_, n227, n260, i_4_, i_5_, i_2_ };
assign n418 = 16'h0080 >> { i_12_, i_1_, i_6_, n207 };
assign n419 = 16'hfff7 >> { i_7_, n37, n211, n321 };
assign n420 = 64'h0880aaaa8880aaaa >> { n418, i_3_, n417, i_2_, n419, n320 };
assign n421 = 64'h15373737153f3f3f >> { n168, n243, n155, n277, n227, n327 };
assign n422 = 64'hf5fdf7fff7fff7ff >> { i_9_, n288, n293, i_6_, i_3_, i_5_ };
assign n423 = 64'h929ab2ba828aa2aa >> { n288, n293, n294, i_6_, i_5_, i_3_ };
assign n28 = 16'ha820 >> { i_9_, i_10_, i_6_, i_1_ };
assign n64 = 32'd1 >> { n34, n35, i_3_, i_10_, i_9_ };
assign n424 = 64'haaaaaa28aaaaaa20 >> { i_9_, n326, n325, i_3_, n423, n261 };
assign n425 = 64'hd7f7dfffdfffdfff >> { i_8_, n310, n313, i_6_, i_5_, i_3_ };
assign n426 = 32'd286347537 >> { n337, n336, n425, n255, n338 };
assign n427 = 64'h2022202000220020 >> { n44, n27, i_8_, n43, n46, n47 };
assign n428 = 64'h555d050d557f050f >> { i_11_, n427, i_0_, i_12_, i_5_, n28 };
assign o_2_ = 64'hfdfdfffdfffdfffd >> { n38, n339, i_11_, n41, n29, n428 };
assign n430 = 64'h3120312075753120 >> { i_10_, n33, n110, n108, i_3_, i_8_ };
assign n431 = 64'h0022202202222222 >> { n99, n49, n430, i_8_, n163, n370 };
assign n432 = 32'd2863327914 >> { n162, n431, n365, n368, i_5_ };
assign n433 = 64'hfdf5fff7fff7fff7 >> { i_0_, n94, n86, i_7_, i_5_, n350 };
assign n65 = 16'hfdec >> { i_11_, i_12_, i_10_, i_7_ };
assign n434 = 64'h0000000000008000 >> { n95, n352, n438, n118, n355, n441 };
assign o_4_ = 64'hffffffffffff7fff >> { n89, n447, n434, n348, n433, n432 };
assign n436 = 64'h0000200000002008 >> { i_13_, i_11_, i_3_, i_9_, i_5_, i_12_ };
assign n437 = 64'ha0e02060a0f12071 >> { n106, i_6_, i_0_, n436, i_1_, i_5_ };
assign n438 = 64'h0000aa2a0000bf7f >> { n349, n100, i_8_, n437, i_7_, i_5_ };
assign n439 = 64'ha8982010a898a898 >> { i_4_, i_3_, i_10_, n356, i_0_, i_2_ };
assign n440 = 64'h8006000680040004 >> { n94, n129, i_6_, i_8_, i_5_, i_0_ };
assign n441 = 64'h0000000200020002 >> { n440, n439, n125, n130, n358, n134 };
assign n442 = 64'ha2aab3bfb3bfb3bf >> { i_6_, n140, n359, i_9_, n360, i_12_ };
assign n443 = 32'd11250603 >> { n141, n140, n143, n142, i_7_ };
assign n66 = 64'h0000000200010003 >> { i_11_, i_12_, i_1_, i_5_, i_10_, i_6_ };
assign n444 = 64'h0000000000000008 >> { n138, n144, n145, n362, n442, n443 };
assign n445 = 64'h4455000544550405 >> { n111, i_3_, n158, n181, n184, n185 };
assign n446 = 64'h22222222f2222222 >> { n183, i_5_, n445, n374, n175, n177 };
assign n447 = 64'haaaaaaaa2aaaaaaa >> { n188, n186, n446, n372, n376, i_0_ };
assign n448 = 64'h0000ff080008ff08 >> { i_2_, i_7_, i_3_, i_10_, i_8_, n182 };
assign n449 = 64'h51115111d9995111 >> { i_12_, n31, i_1_, n30, i_3_, i_6_ };
assign n450 = 64'h0011011101110111 >> { n449, n448, i_11_, n241, n238, n237 };
assign n451 = 64'h0100044002200880 >> { i_6_, i_7_, i_0_, i_5_, i_2_, i_1_ };
assign n452 = 32'd4223384507 >> { n53, i_8_, n451, n400, n242 };
assign n453 = 64'h9810fa50fc30fe70 >> { i_2_, i_1_, n295, n169, i_6_, i_7_ };
assign n67 = 16'h0111 >> { i_1_, i_6_, i_2_, i_5_ };
assign n454 = 64'hff7fff7fffffff7f >> { i_0_, n453, n296, n297, n299, n404 };
assign n455 = 32'd65793 >> { n266, n454, n281, n407, n410 };
assign n456 = 64'h0200020002020200 >> { i_12_, i_8_, i_3_, i_13_, i_9_, i_11_ };
assign n457 = 64'hfffd77fdfdfd75fd >> { n319, n302, n416, i_10_, i_3_, n456 };
assign n458 = 64'h0008000000080008 >> { n412, i_3_, n307, n415, n457, n420 };
assign n459 = 64'h77f77fff7fff7fff >> { i_9_, n288, n293, i_3_, i_6_, i_5_ };
assign n460 = 16'hd555 >> { n459, n328, n421, n250 };
assign n461 = 64'h7fff7fff6eee7fff >> { i_6_, n277, i_10_, n323, i_7_, i_8_ };
assign n462 = 64'h22ffa2ff20ffa0ff >> { i_8_, n97, n99, n461, n266, n422 };
assign n463 = 64'h0000000000000080 >> { n329, n332, n424, n462, n426, n460 };
assign n68 = 64'h0101010111010101 >> { i_12_, i_7_, n55, n65, i_2_, i_9_ };
assign n69 = 32'd4160223061 >> { i_10_, i_9_, i_3_, n49, i_4_ };
assign n70 = 8'h08 >> { i_9_, i_8_, i_4_ };
assign n71 = 16'h8cae >> { i_1_, i_2_, i_6_, i_7_ };
assign n72 = 64'h5500554055405540 >> { i_1_, i_6_, n74, n53, n73, i_5_ };
assign n73 = 4'h1 >> { i_10_, i_7_ };
assign n29 = 16'ha820 >> { i_9_, i_10_, i_5_, i_0_ };
assign n74 = 32'd2 >> { i_10_, i_8_, i_2_, i_1_, i_4_ };
assign n75 = 4'h2 >> { n76, n346 };
assign n76 = 8'h45 >> { n78, n77, i_0_ };
assign n77 = 64'h0000000200800082 >> { i_9_, i_10_, i_2_, i_6_, i_8_, i_4_ };
assign n78 = 64'hfffffffdff7fff7d >> { i_9_, i_10_, i_3_, i_6_, i_7_, i_4_ };
assign n79 = 64'h0000000000000008 >> { i_3_, i_9_, i_2_, i_0_, i_6_, i_4_ };
assign n80 = 64'h0055045501550555 >> { i_11_, i_12_, n81, i_1_, i_6_, i_0_ };
assign n81 = 32'd353703168 >> { i_2_, n83, n70, n82, n62 };
assign n82 = 4'h8 >> { i_6_, i_7_ };
assign n83 = 64'hfffffd75febafc30 >> { i_11_, i_12_, i_9_, i_10_, i_6_, i_7_ };
assign n30 = 4'h2 >> { i_8_, i_10_ };
assign n84 = 32'd538976800 >> { i_8_, n49, n85, i_10_, i_4_ };
assign n85 = 64'h0001000100011111 >> { i_7_, i_1_, i_6_, i_2_, i_3_, i_0_ };
assign n86 = 64'hf5f7fcfff7f7feff >> { i_4_, n88, n87, i_0_, i_1_, i_3_ };
assign n87 = 16'h0002 >> { i_10_, i_13_, i_11_, i_12_ };
assign n88 = 8'h08 >> { i_12_, i_10_, i_11_ };
assign n89 = 32'd572662274 >> { n92, n91, n90, i_12_, n93 };
assign n90 = 32'd3722436575 >> { i_8_, i_3_, i_7_, i_11_, i_9_ };
assign n91 = 8'h08 >> { i_4_, i_5_, i_3_ };
assign n92 = 8'h02 >> { i_7_, i_11_, i_10_ };
assign n93 = 8'h08 >> { i_0_, i_1_, i_2_ };
assign n31 = 4'h8 >> { i_8_, i_9_ };
assign n94 = 4'h8 >> { i_10_, i_11_ };
assign n95 = 64'h88888888888888a8 >> { i_4_, n98, i_5_, i_6_, n97, n96 };
assign n96 = 4'h2 >> { i_11_, i_12_ };
assign n97 = 64'h0000000000008000 >> { i_8_, i_5_, i_3_, i_6_, i_7_, i_10_ };
assign n98 = 64'h00f7f7f7f7f7f7f7 >> { i_7_, i_10_, i_8_, i_0_, i_2_, i_3_ };
assign n99 = 8'h02 >> { i_2_, i_1_, i_0_ };
assign n100 = 64'haa20202020202020 >> { n31, n101, i_3_, n103, n102, n104 };
assign n101 = 4'h1 >> { i_6_, i_7_ };
assign n102 = 64'hf7f7f7f7f7f700f7 >> { i_7_, i_8_, i_9_, i_0_, i_2_, i_3_ };
assign n103 = 4'h1 >> { i_6_, i_4_ };
assign o_1_ = 64'h666566656665aaa9 >> { n30, n31, n34, n35, i_3_, n33 };
assign n104 = 8'h08 >> { i_12_, i_5_, i_11_ };
assign n105 = 4'h2 >> { i_4_, i_3_ };
assign n106 = 64'hfdfffdfffdfffdfd >> { i_3_, i_12_, i_4_, i_9_, i_13_, i_11_ };
assign n107 = 16'h0008 >> { i_0_, i_11_, i_2_, i_1_ };
assign n108 = 8'h02 >> { i_13_, i_12_, i_11_ };
assign n109 = 64'h0000000200020002 >> { i_1_, i_6_, i_3_, i_7_, i_10_, i_8_ };
assign n110 = 8'h01 >> { i_10_, i_13_, i_11_ };
assign n111 = 8'h01 >> { i_9_, i_13_, i_12_ };
assign n112 = 4'h8 >> { n113, i_12_ };
assign n113 = 4'h2 >> { i_13_, i_11_ };
assign n33 = 4'h2 >> { i_13_, i_4_ };
assign n114 = 64'hdddfdddf5555dddf >> { n117, i_2_, n116, n115, i_5_, i_0_ };
assign n115 = 32'd32768 >> { i_8_, i_10_, i_3_, i_12_, i_11_ };
assign n116 = 64'h0080008000000080 >> { i_12_, i_6_, i_7_, i_2_, i_10_, i_11_ };
assign n117 = 32'd2012708863 >> { i_11_, i_12_, i_6_, i_10_, i_9_ };
assign n118 = 32'd221196079 >> { n55, n124, n119, i_2_, n57 };
assign n119 = 64'h80888088aaaa8088 >> { n120, n104, n122, n121, n96, n123 };
assign n120 = 64'he8eaeceef8fafcff >> { i_1_, i_2_, i_3_, i_6_, i_7_, i_8_ };
assign n121 = 16'h0080 >> { i_5_, i_6_, i_2_, i_8_ };
assign n122 = 64'hdddddfffdfffdfff >> { i_8_, i_1_, i_3_, i_6_, i_5_, i_7_ };
assign n123 = 4'h1 >> { i_0_, i_4_ };
endmodule

655
openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act Normal file
View File

@ -0,0 +1,655 @@
i_0_ 0.517800 0.509800
i_1_ 0.507400 0.499600
i_2_ 0.508800 0.498400
i_3_ 0.478800 0.507400
i_4_ 0.491600 0.501200
i_5_ 0.499600 0.504400
i_6_ 0.494200 0.516000
i_7_ 0.502600 0.504000
i_8_ 0.510400 0.482400
i_9_ 0.516800 0.499800
i_10_ 0.493000 0.507200
i_11_ 0.495600 0.504600
i_12_ 0.502800 0.507600
i_13_ 0.494600 0.500600
i_14_ 0.504800 0.502800
i_15_ 0.487600 0.495200
i_16_ 0.504000 0.505200
i_17_ 0.497400 0.512600
i_18_ 0.502200 0.502200
i_19_ 0.495200 0.500000
i_20_ 0.491000 0.493200
i_21_ 0.495600 0.501600
i_22_ 0.495200 0.503200
i_23_ 0.505400 0.491000
i_24_ 0.518400 0.508200
i_25_ 0.502400 0.500800
i_26_ 0.494600 0.494600
i_27_ 0.497000 0.486400
i_28_ 0.500400 0.500600
i_29_ 0.503400 0.500800
i_30_ 0.489000 0.511800
i_31_ 0.495400 0.503000
i_32_ 0.481000 0.510800
i_33_ 0.500800 0.501600
i_34_ 0.498400 0.496200
i_35_ 0.512400 0.485400
i_36_ 0.493000 0.499400
i_37_ 0.497000 0.501000
i_38_ 0.505800 0.501600
n45 0.000600 0.025535
n46 0.007400 0.237365
n47 0.016000 0.000507
n48 0.006400 0.000028
n49 0.123000 0.026212
n50 0.500600 0.125514
n51 0.122000 0.026567
n52 0.239600 0.095360
n53 0.016000 0.004553
n54 0.246800 0.094778
n55 0.134400 0.030214
n56 0.244200 0.089975
n57 0.995200 0.000000
n58 0.000000 0.000000
n59 0.997800 0.025852
n60 0.128000 0.029538
n61 0.058400 0.007102
n62 0.123000 0.025653
n63 0.962800 0.090969
n64 0.252200 0.094921
n65 0.067000 0.006902
n66 0.000000 0.000000
n67 0.008200 0.237452
n68 0.015400 0.000489
n69 0.016000 0.000444
n70 0.241000 0.098188
n71 0.124000 0.026377
n72 0.261000 0.089271
n73 0.125400 0.025966
n74 0.260000 0.099153
n75 0.234000 0.097721
n76 0.242600 0.092149
n77 0.063800 0.008474
n78 0.969400 0.000965
n79 0.003600 0.121985
n80 0.000000 0.000464
n81 0.000200 0.000006
n82 0.125400 0.026450
n83 0.243400 0.094495
n84 0.125000 0.026618
n85 0.997400 0.000000
n86 0.000000 0.000015
n87 0.117600 0.026356
n88 0.128800 0.029209
n89 0.244800 0.102081
n90 0.015000 0.000426
n91 0.002800 0.236969
n92 0.123800 0.027757
n93 0.030400 0.001734
n94 0.057800 0.006902
n95 0.000200 0.000000
n96 0.113000 0.024458
n97 0.122200 0.025590
n98 0.015400 0.000472
n99 0.128200 0.027168
n100 0.016200 0.000474
n101 0.001600 0.000010
n102 0.250200 0.091886
n103 0.031200 0.001879
n104 0.184400 0.031650
n105 0.129200 0.028722
n106 0.000000 0.000000
n107 0.012200 0.000510
n108 0.117600 0.028205
n109 0.995000 0.000000
n110 0.000200 0.000050
n111 0.999400 0.000474
n112 0.122000 0.028443
n113 0.061600 0.006943
n114 0.014600 0.000454
n115 0.015800 0.000444
n116 0.008000 0.005167
n117 0.126800 0.026916
n118 0.997200 0.000068
n119 0.019200 0.000431
n120 0.186000 0.007014
n121 0.014600 0.000464
n122 0.232200 0.017175
n123 0.018200 0.000443
n124 0.995600 0.001698
n125 0.015200 0.000482
n126 0.063800 0.007433
n127 0.118200 0.025867
n128 0.033400 0.002072
n129 0.015800 0.000501
n130 0.000000 0.000000
n131 0.000000 0.000000
n132 0.007000 0.000111
n133 0.059000 0.007017
n134 0.991000 0.000001
n135 0.014200 0.000485
n136 0.129000 0.028071
n137 0.033400 0.002054
n138 0.991800 0.000063
n139 0.996400 0.000000
n140 0.003000 0.000025
n141 0.242000 0.089340
n142 0.014600 0.000529
n143 0.996800 0.000429
n144 0.115000 0.025850
n145 0.129200 0.026603
n146 0.123000 0.027116
n147 0.016600 0.000492
n148 0.031000 0.002016
n149 0.054800 0.006993
n150 0.002400 0.000009
n151 0.132600 0.029850
n152 0.032200 0.001795
n153 0.014400 0.000444
n154 0.982200 0.003292
n155 0.111400 0.025404
n156 0.011400 0.000444
n157 0.006600 0.000057
n158 0.010400 0.000358
n159 0.134000 0.010573
n160 0.122200 0.028002
n161 0.077000 0.007987
n162 0.277200 0.152811
n163 0.129600 0.028505
n164 0.257400 0.100855
n165 0.032800 0.001762
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# Benchmark "ex5p" written by ABC on Tue Mar 12 09:27:13 2019
.model ex5p
.inputs i_0_ i_1_ i_2_ i_3_ i_4_ i_5_ i_6_ i_7_
.outputs o_0_ o_1_ o_2_ o_3_ o_4_ o_5_ o_6_ o_7_ o_8_ o_9_ o_10_ o_11_ \
o_12_ o_13_ o_14_ o_15_ o_16_ o_17_ o_18_ o_19_ o_20_ o_21_ o_22_ o_23_ \
o_24_ o_25_ o_26_ o_27_ o_28_ o_29_ o_30_ o_31_ o_32_ o_33_ o_34_ o_35_ \
o_36_ o_37_ o_38_ o_39_ o_40_ o_41_ o_42_ o_43_ o_44_ o_45_ o_46_ o_47_ \
o_48_ o_49_ o_50_ o_51_ o_52_ o_53_ o_54_ o_55_ o_56_ o_57_ o_58_ o_59_ \
o_60_ o_61_ o_62_
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.names i_3_ i_4_ i_5_ n199
000 1
.names i_3_ i_5_ i_4_ n200
110 1
.names i_0_ i_4_ i_5_ i_3_ i_1_ i_2_ n201
111000 1
.names n206 n205 n204 n202
111 1
.names i_4_ n75 i_3_ i_5_ i_6_ n203
0-0-- 1
0--10 1
-0--- 1
.names n183 i_4_ n78 i_5_ n204
00-- 1
--10 1
.names n78 n80 n117 n205
0-- 1
-00 1
.names n207 n158 n90 n92 n206
000- 1
00-0 1
.names i_3_ i_4_ i_5_ i_2_ i_0_ i_1_ n207
111100 1
.names o_4_ n103 n113 n76 n185 n208
00--- 1
0-000 1
.names n86 n78 n113 n76 n209
00-- 1
0-00 1
.names n115 n76 n210
11 1
.names o_5_ n78 n98 n108 n211
00-- 1
0-00 1
.names n213 n297 n148 o_36_
111 0
.names n214 n204 n160 n203 n213
1111 1
.names n115 i_3_ i_6_ n214
0-- 1
-11 1
.names n216 n194 n193 n138 n188 n137 n215
111110 1
.names n135 n90 n146 n133 n216
00-- 1
0-10 1
.names n219 n218 n144 n217
111 1
.names n108 n161 n75 n103 n181 n218
1---- 0
-01-- 0
---10 0
.names n76 n103 n219
11 0
.names n90 n97 n220
00 1
.names n113 n98 n221
00 1
.names i_3_ i_4_ n78 n97 n222
001- 0
11-1 0
.names o_19_ n115 n113 n76 n223
00-- 1
0-00 1
.names n75 i_3_ i_6_ i_4_ n224
10-- 0
1-00 0
.names n189 n208 n226 n133 o_39_
1110 0
.names n140 n227 n141 n226
110 1
.names n78 n98 n117 n227
00- 1
1-0 1
.names n103 n132 n78 n80 n117 n228
1--1- 0
1---1 0
-11-- 0
.names n296 n141 n234 n232 n230 n108 o_40_
111110 0
.names n231 n175 n157 n98 n230
1110 1
.names n109 n97 n115 n92 n76 n231
000-- 1
00-00 1
.names n233 n128 n138 n137 n115 n113 n232
11100- 1
1110-0 1
.names n75 n76 n113 n233
0-- 1
-00 1
.names n237 n236 n177 n235 n234
1110 1
.names n101 n76 n235
11 1
.names n101 n133 n113 n236
0-- 1
-00 1
.names i_3_ n103 i_6_ i_4_ i_5_ i_7_ n237
11---- 0
1-1000 0
.names n239 n222 n238
11 1
.names n78 i_3_ i_4_ i_5_ n239
101- 0
11-0 0
.names i_5_ i_4_ i_3_ i_6_ i_7_ n240
1001- 1
100-1 1
.names n244 n243 n242 n169 n210 n241
11100 1
.names n75 n117 n80 n242
0-- 1
-00 1
.names n101 n80 n93 n161 n243
11-- 0
--10 0
.names n186 i_0_ i_2_ n113 n95 n244
011-- 0
10-1- 0
10--1 0
.names n201 n109 n78 n173 n245
000- 1
00-0 1
.names n92 n103 n161 n246
00- 1
0-1 1
.names n198 n76 i_1_ n103 n186 n161 n247
10--11 1
1-00-- 1
-100-- 1
.names n211 n228 n248
11 1
.names n115 n117 n80 n249
0-- 1
-00 1
.names n187 n127 n253 n251 i_3_ i_2_ o_46_
111100 0
.names n252 n172 n169 n92 n251
1100 1
.names n90 n76 n117 n252
0-- 1
-00 1
.names n211 n239 n228 n222 n253
1111 1
.names n259 n317 n257 n255 n234 o_47_
11111 0
.names n193 n97 n146 n256 n153 n255
10-11 1
111-- 1
.names n129 n166 n93 n256
00- 1
1-0 1
.names n228 n211 n258 n209 n201 n257
11110 1
.names n103 n186 n181 n258
0-- 1
-11 1
.names n90 n260 o_10_ n259
000 1
.names n121 n97 n260
11 1
.names n169 n210 o_48_
00 1
.names n263 n214 n253 n220 n148 o_49_
11111 0
.names i_4_ i_6_ i_3_ n263
00- 1
1-0 1
.names i_6_ i_7_ i_5_ i_4_ n264
1100 1
.names n237 n268 n266 n257 n150 o_51_
11111 0
.names n267 n101 n161 n113 n76 n266
10--- 1
1-100 1
.names i_5_ i_4_ i_3_ i_6_ i_7_ n267
0001- 0
1000- 0
-0010 0
.names n206 n221 n138 n269 o_8_ o_18_ n268
111100 1
.names n115 i_3_ i_5_ i_4_ n269
10-- 0
1-10 0
.names n217 n269 n275 n319 n271 n113 o_52_
111110 0
.names n272 n131 n134 n97 n271
1110 1
.names i_3_ i_4_ i_5_ i_7_ n78 i_6_ n272
1010-- 0
101--0 0
10-11- 0
110-1- 0
.names n103 n113 n273
11 0
.names n166 o_4_ n92 n93 n274
000- 1
00-0 1
.names n246 n236 n267 n235 n275
1110 1
.names n245 n236 n228 n182 n208 n260 n276
111110 1
.names n272 n95 n103 n277
100 1
.names n249 n279 n224 n223 n169 n278
11110 1
.names n158 n171 n113 n279
000 1
.names n141 n281 n103 n78 n280
1100 1
.names n90 i_3_ i_5_ i_4_ n281
1010 0
1100 0
.names i_3_ i_4_ n93 i_6_ i_5_ n282
10-10 0
1-1-- 0
-11-- 0
.names n284 n214 n203 n283
111 1
.names n199 n75 n155 n284
001 0
11- 0
.names n138 n115 n285
10 1
.names n145 n188 n286
11 1
.names n234 n288 n257 n255 n314 n169 o_58_
111110 0
.names n214 o_15_ n288
10 1
.names n92 n103 n185 n98 n289
00-- 1
0-00 1
.names n237 n291 n278 n266 n257 n150 o_60_
111111 0
.names n274 n243 o_11_ o_7_ n184 n291
11000 1
.names n294 n286 n285 n257 n150 n293 o_61_
111111 0
.names n130 n128 n93 n293
110 1
.names n289 n273 n207 n158 n294
1100 1
.names n314 i_1_ n275 i_3_ o_62_
1110 0
.names i_2_ i_1_ i_0_ n186 n182 n296
010-- 0
01-1- 0
1010- 0
----0 0
.names n209 i_1_ n121 i_0_ i_2_ n80 n297
100-1- 1
100--0 1
10-0-- 1
.names n201 n76 n173 n155 n103 n186 n298
00000- 1
0000-1 1
.names n217 n215 n338 n97 n146 n92 o_37_
1110-- 0
111-10 0
.names n224 n223 n222 n221 n220 n80 n300
111110 1
.names n300 n127 n115 n161 i_5_ n95 o_38_
110--- 0
11-100 0
.names n113 n101 i_3_ i_6_ i_5_ i_4_ n302
0-0--- 1
0--100 1
-0---- 1
.names n220 n218 n214 n302 i_2_ n303
11110 1
.names n238 n232 n303 o_41_
111 0
.names i_3_ i_5_ i_7_ i_6_ n103 n93 n305
01---- 1
0---00 1
10-1-- 1
-10--- 1
.names n249 n211 n205 n154 n158 i_4_ n306
111100 1
.names n241 n340 n306 n305 o_42_
1111 0
.names n113 n75 n95 n90 n121 n101 n308
11---- 0
1--1-- 0
-11--- 0
----11 0
.names n101 n184 n183 n240 n309
011- 1
0-10 1
1-0- 1
-000 1
.names n227 n97 n117 i_4_ n92 n76 n310
10---- 1
1-0000 1
.names n340 n247 n241 n157 n131 n310 o_43_
111111 0
.names n188 i_3_ i_6_ i_4_ i_5_ n78 n312
1000-- 1
11-11- 1
1-001- 1
1----0 1
.names n314 n248 n168 n127 n312 o_44_
11111 0
.names n178 n155 i_1_ i_2_ i_0_ n92 n314
1000-- 1
1011-0 1
10--1- 1
.names n97 n78 n121 n113 n98 n92 n315
00---- 1
1-0000 1
.names n249 n159 n127 n315 n90 n75 o_45_
111100 0
.names n192 i_1_ i_0_ i_4_ i_5_ i_2_ n317
11---- 1
1-1--- 1
1--000 1
.names n117 n161 n121 n129 n101 n93 n318
0100-- 1
010-0- 1
0--0-0 1
0---00 1
.names n274 n318 i_1_ i_0_ i_2_ n113 n319
111--- 1
11-0-- 1
11--10 1
.names i_1_ i_2_ n92 i_0_ i_3_ i_4_ n320
000--- 0
111--- 0
11-01- 0
11-101 0
1-1001 0
-00001 0
.names n278 n277 n276 n176 n320 o_53_
11111 0
.names n92 n90 n167 n166 n113 n97 n322
01--0- 1
01---0 1
0-000- 1
-000-0 1
.names n203 n322 n97 n121 n78 n98 n323
11000- 1
1110-0 1
.names n285 n277 n276 n176 n323 o_55_
11111 0
.names n98 n181 n97 n113 n76 n80 n325
0-0--0 1
11100- 1
-11000 1
.names n284 n223 n206 n325 n169 n152 n326
111100 1
.names n286 n248 n238 n127 n326 o_56_
11111 0
.names i_1_ i_0_ i_2_ n76 n152 i_6_ n328
100--0 0
1101-- 0
---01- 0
.names n289 n228 n203 n195 o_19_ n92 n329
111100 1
.names n319 n271 n189 n329 n328 o_59_
11111 0
.names n165 n143 n161 n76 n103 n93 n331
110-00 1
1110-- 1
.names n195 n193 n113 n115 n97 n101 n332
110--- 1
11-000 1
.names n202 n197 n189 n332 n331 o_34_
11111 0
.names i_5_ i_4_ i_3_ n78 i_7_ i_6_ n334
0101-- 0
100111 0
111--- 0
.names n211 n188 n334 n210 n75 i_3_ n335
1100-1 1
11100- 1
.names n297 n160 n148 n335 o_35_
1111 0
.names i_3_ n200 i_2_ i_1_ i_4_ i_0_ n337
001--- 1
1-0-1- 1
-001-- 1
-0--0- 1
--00-1 1
.names n298 n178 n175 n153 n337 n113 n338
111110 1
.names i_3_ n75 i_6_ i_5_ i_4_ i_7_ n339
0111-1 0
01--1- 0
11000- 0
1-1000 0
.names n309 n308 n339 n179 n166 n340
11100 1
.names n264 n237 i_2_ i_1_ i_0_ n76 n341
110-0- 1
110--0 1
11-0-- 1
.names n317 n257 n177 n154 n153 n341 o_50_
111111 0
.names n282 n184 n129 n97 n80 n101 n343
1000-0 1
100-0- 1
1--10- 1
.names n267 n196 n101 n133 n113 n76 n344
100--- 1
10-000 1
.names n343 n283 n280 n344 n135 o_54_
11110 0
.names n184 n97 n121 n113 i_4_ n76 n346
00---- 1
0-0000 1
.names n195 n190 n154 n171 n135 o_25_ n347
111000 1
.names n280 n232 n347 n346 n115 o_57_
11110 0
.end

562
openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v Normal file
View File

@ -0,0 +1,562 @@
/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
module ex5p(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_, o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_, o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_, o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_, o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_, o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_, o_61_, o_62_);
input i_0_;
input i_1_;
input i_2_;
input i_3_;
input i_4_;
input i_5_;
input i_6_;
input i_7_;
wire n101;
wire n103;
wire n108;
wire n109;
wire n113;
wire n115;
wire n117;
wire n120;
wire n121;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
wire n200;
wire n201;
wire n202;
wire n203;
wire n204;
wire n205;
wire n206;
wire n207;
wire n208;
wire n209;
wire n210;
wire n211;
wire n213;
wire n214;
wire n215;
wire n216;
wire n217;
wire n218;
wire n219;
wire n220;
wire n221;
wire n222;
wire n223;
wire n224;
wire n226;
wire n227;
wire n228;
wire n230;
wire n231;
wire n232;
wire n233;
wire n234;
wire n235;
wire n236;
wire n237;
wire n238;
wire n239;
wire n240;
wire n241;
wire n242;
wire n243;
wire n244;
wire n245;
wire n246;
wire n247;
wire n248;
wire n249;
wire n251;
wire n252;
wire n253;
wire n255;
wire n256;
wire n257;
wire n258;
wire n259;
wire n260;
wire n263;
wire n264;
wire n266;
wire n267;
wire n268;
wire n269;
wire n271;
wire n272;
wire n273;
wire n274;
wire n275;
wire n276;
wire n277;
wire n278;
wire n279;
wire n280;
wire n281;
wire n282;
wire n283;
wire n284;
wire n285;
wire n286;
wire n288;
wire n289;
wire n291;
wire n293;
wire n294;
wire n296;
wire n297;
wire n298;
wire n300;
wire n302;
wire n303;
wire n305;
wire n306;
wire n308;
wire n309;
wire n310;
wire n312;
wire n314;
wire n315;
wire n317;
wire n318;
wire n319;
wire n320;
wire n322;
wire n323;
wire n325;
wire n326;
wire n328;
wire n329;
wire n331;
wire n332;
wire n334;
wire n335;
wire n337;
wire n338;
wire n339;
wire n340;
wire n341;
wire n343;
wire n344;
wire n346;
wire n347;
wire n75;
wire n76;
wire n78;
wire n80;
wire n83;
wire n86;
wire n90;
wire n92;
wire n93;
wire n95;
wire n97;
wire n98;
output o_0_;
output o_10_;
output o_11_;
output o_12_;
output o_13_;
output o_14_;
output o_15_;
output o_16_;
output o_17_;
output o_18_;
output o_19_;
output o_1_;
output o_20_;
output o_21_;
output o_22_;
output o_23_;
output o_24_;
output o_25_;
output o_26_;
output o_27_;
output o_28_;
output o_29_;
output o_2_;
output o_30_;
output o_31_;
output o_32_;
output o_33_;
output o_34_;
output o_35_;
output o_36_;
output o_37_;
output o_38_;
output o_39_;
output o_3_;
output o_40_;
output o_41_;
output o_42_;
output o_43_;
output o_44_;
output o_45_;
output o_46_;
output o_47_;
output o_48_;
output o_49_;
output o_4_;
output o_50_;
output o_51_;
output o_52_;
output o_53_;
output o_54_;
output o_55_;
output o_56_;
output o_57_;
output o_58_;
output o_59_;
output o_5_;
output o_60_;
output o_61_;
output o_62_;
output o_6_;
output o_7_;
output o_8_;
output o_9_;
assign o_6_ = 4'h8 >> { n75, n76 };
assign n83 = 4'h1 >> { i_6_, i_7_ };
assign n173 = 32'd2 >> { i_5_, i_4_, i_6_, i_7_, i_3_ };
assign n174 = 16'h0008 >> { n76, n78, n175, n141 };
assign n175 = 8'h57 >> { n80, n117, n103 };
assign n176 = 16'h222a >> { n129, n133, n103, n177 };
assign n177 = 64'haaffaafbaafbaafb >> { i_7_, i_6_, n101, i_4_, i_5_, i_3_ };
assign n178 = 32'd286331217 >> { n80, n179, n181, n97, n180 };
assign n179 = 32'd40 >> { i_4_, i_3_, i_6_, i_7_, i_5_ };
assign n180 = 64'h0000000000008000 >> { i_2_, i_0_, i_1_, i_5_, i_4_, i_3_ };
assign n181 = 32'd4294705145 >> { i_7_, i_4_, i_3_, i_6_, i_5_ };
assign n182 = 32'd1970602101 >> { n183, n184, n146, n133, n90 };
assign o_2_ = 16'h0008 >> { i_4_, i_3_, n83, i_5_ };
assign n183 = 4'h8 >> { i_6_, i_7_ };
assign n184 = 64'h0000000000000080 >> { i_5_, i_4_, i_3_, i_2_, i_1_, i_0_ };
assign n185 = 8'h08 >> { i_3_, i_4_, i_5_ };
assign n186 = 32'd3452816861 >> { i_6_, i_7_, i_5_, i_3_, i_4_ };
assign n187 = 8'h02 >> { o_19_, n75, n188 };
assign n188 = 8'hfd >> { i_4_, i_3_, n115 };
assign n189 = 16'h0080 >> { n191, n190, n160, n192 };
assign n190 = 64'heeffeeefeeefeeef >> { i_7_, i_6_, n101, i_5_, i_3_, i_4_ };
assign n191 = 8'h8a >> { n140, n95, n103 };
assign n192 = 32'd1431655767 >> { n117, n185, n80, n76, n115 };
assign o_3_ = 4'h2 >> { i_7_, n86 };
assign n193 = 16'h1bbb >> { n101, i_4_, n93, i_3_ };
assign n194 = 16'h0ddd >> { n113, n101, n161, n93 };
assign n195 = 8'h15 >> { n133, n101, n196 };
assign n196 = 32'd128 >> { i_2_, i_3_, i_0_, i_4_, i_1_ };
assign n197 = 32'd32768 >> { o_18_, n134, n151, n198, n131 };
assign n198 = 32'd2178264063 >> { n103, n200, i_6_, i_7_, n199 };
assign n199 = 8'h01 >> { i_5_, i_4_, i_3_ };
assign n200 = 8'h08 >> { i_4_, i_5_, i_3_ };
assign n201 = 64'h0000000000000080 >> { i_2_, i_1_, i_3_, i_5_, i_4_, i_0_ };
assign n202 = 8'h80 >> { n204, n205, n206 };
assign n86 = 16'h0008 >> { i_4_, i_6_, i_3_, i_5_ };
assign n203 = 32'd926381879 >> { i_6_, i_5_, i_3_, n75, i_4_ };
assign n204 = 16'h11f1 >> { i_5_, n78, i_4_, n183 };
assign n205 = 8'h57 >> { n117, n80, n78 };
assign n206 = 16'h0111 >> { n92, n90, n158, n207 };
assign n207 = 64'h0000000000008000 >> { i_1_, i_0_, i_2_, i_5_, i_4_, i_3_ };
assign n208 = 32'd286331157 >> { n185, n76, n113, n103, o_4_ };
assign n209 = 16'h1115 >> { n76, n113, n78, n86 };
assign n210 = 4'h8 >> { n76, n115 };
assign n211 = 16'h1115 >> { n108, n98, n78, o_5_ };
assign o_36_ = 8'h7f >> { n148, n297, n213 };
assign o_4_ = 32'd8 >> { i_5_, i_4_, i_7_, i_6_, i_3_ };
assign n213 = 16'h8000 >> { n203, n160, n204, n214 };
assign n214 = 8'hd5 >> { i_6_, i_3_, n115 };
assign n215 = 64'h0000000080000000 >> { n137, n188, n138, n193, n194, n216 };
assign n216 = 16'h1151 >> { n133, n146, n90, n135 };
assign n217 = 8'h80 >> { n144, n218, n219 };
assign n218 = 32'd1162149957 >> { n181, n103, n75, n161, n108 };
assign n219 = 4'h7 >> { n103, n76 };
assign n220 = 4'h1 >> { n97, n90 };
assign n221 = 4'h1 >> { n98, n113 };
assign n222 = 16'h67ef >> { n97, n78, i_4_, i_3_ };
assign o_5_ = 16'h0008 >> { i_4_, i_7_, i_6_, i_5_ };
assign n223 = 16'h1115 >> { n76, n113, n115, o_19_ };
assign n224 = 16'hddd5 >> { i_4_, i_6_, i_3_, n75 };
assign o_39_ = 16'hff7f >> { n133, n226, n208, n189 };
assign n226 = 8'h08 >> { n141, n227, n140 };
assign n227 = 8'h1b >> { n117, n98, n78 };
assign n228 = 32'd353703231 >> { n117, n80, n78, n132, n103 };
assign o_40_ = 64'hffffffff7fffffff >> { n108, n230, n232, n234, n141, n296 };
assign n230 = 16'h0080 >> { n98, n157, n175, n231 };
assign n231 = 32'd16843025 >> { n76, n92, n115, n97, n109 };
assign n232 = 64'h0000008000800080 >> { n113, n115, n137, n138, n128, n233 };
assign o_7_ = 64'h0000000000008000 >> { i_4_, i_3_, n90, i_5_, i_6_, i_7_ };
assign n233 = 8'h57 >> { n113, n76, n75 };
assign n234 = 16'h0080 >> { n235, n177, n236, n237 };
assign n235 = 4'h8 >> { n76, n101 };
assign n236 = 8'h57 >> { n113, n133, n101 };
assign n237 = 64'h7777777777777757 >> { i_7_, i_5_, i_4_, i_6_, n103, i_3_ };
assign n238 = 4'h8 >> { n222, n239 };
assign n239 = 16'hdf57 >> { i_5_, i_4_, i_3_, n78 };
assign n240 = 32'd33686016 >> { i_7_, i_6_, i_3_, i_4_, i_5_ };
assign n241 = 32'd128 >> { n210, n169, n242, n243, n244 };
assign n242 = 8'h57 >> { n80, n117, n75 };
assign n90 = 8'h02 >> { i_2_, i_0_, i_1_ };
assign n243 = 16'h7707 >> { n161, n93, n80, n101 };
assign n244 = 32'd2644352447 >> { n95, n113, i_2_, i_0_, n186 };
assign n245 = 16'h0111 >> { n173, n78, n109, n201 };
assign n246 = 8'h51 >> { n161, n103, n92 };
assign n247 = 64'h222e000e000e000e >> { n161, n186, n103, i_1_, n76, n198 };
assign n248 = 4'h8 >> { n228, n211 };
assign n249 = 8'h57 >> { n80, n117, n115 };
assign o_46_ = 64'hffffffffffff7fff >> { i_2_, i_3_, n251, n253, n127, n187 };
assign n251 = 16'h0008 >> { n92, n169, n172, n252 };
assign n252 = 8'h57 >> { n117, n76, n90 };
assign o_8_ = 4'h8 >> { n92, n93 };
assign n253 = 16'h8000 >> { n222, n228, n239, n211 };
assign o_47_ = 32'd2147483647 >> { n234, n255, n257, n317, n259 };
assign n255 = 32'd2726330496 >> { n153, n256, n146, n97, n193 };
assign n256 = 8'h1b >> { n93, n166, n129 };
assign n257 = 32'd32768 >> { n201, n209, n258, n211, n228 };
assign n258 = 8'hd5 >> { n181, n186, n103 };
assign n259 = 8'h01 >> { o_10_, n260, n90 };
assign n260 = 4'h8 >> { n97, n121 };
assign o_48_ = 4'h1 >> { n210, n169 };
assign o_49_ = 32'd2147483647 >> { n148, n220, n253, n214, n263 };
assign n92 = 32'd128 >> { i_4_, i_3_, i_5_, i_6_, i_7_ };
assign n263 = 8'h1b >> { i_3_, i_6_, i_4_ };
assign n264 = 16'h0008 >> { i_4_, i_5_, i_7_, i_6_ };
assign o_51_ = 32'd2147483647 >> { n150, n257, n266, n268, n237 };
assign n266 = 32'd572662434 >> { n76, n113, n161, n101, n267 };
assign n267 = 32'd4278058237 >> { i_7_, i_6_, i_3_, i_4_, i_5_ };
assign n268 = 64'h0000000000008000 >> { o_18_, o_8_, n269, n138, n221, n206 };
assign n269 = 16'hdd5d >> { i_4_, i_5_, i_3_, n115 };
assign o_52_ = 64'hffffffff7fffffff >> { n113, n271, n319, n275, n269, n217 };
assign n271 = 16'h0080 >> { n97, n134, n131, n272 };
assign n272 = 64'hd5d7ffdfd5d7dfdf >> { i_6_, n78, i_7_, i_5_, i_4_, i_3_ };
assign n75 = 8'h02 >> { i_1_, i_0_, i_2_ };
assign n93 = 8'h80 >> { i_2_, i_1_, i_0_ };
assign n273 = 4'h7 >> { n113, n103 };
assign n274 = 16'h0111 >> { n93, n92, o_4_, n166 };
assign n275 = 16'h0080 >> { n235, n267, n236, n246 };
assign n276 = 64'h0000000080000000 >> { n260, n208, n182, n228, n236, n245 };
assign n277 = 8'h02 >> { n103, n95, n272 };
assign n278 = 32'd32768 >> { n169, n223, n224, n279, n249 };
assign n279 = 8'h01 >> { n113, n171, n158 };
assign n280 = 16'h0008 >> { n78, n103, n281, n141 };
assign n281 = 16'hffd7 >> { i_4_, i_5_, i_3_, n90 };
assign n282 = 32'd522132767 >> { i_5_, i_6_, n93, i_4_, i_3_ };
assign o_9_ = 4'h8 >> { n75, n95 };
assign n283 = 8'h80 >> { n203, n214, n284 };
assign n284 = 8'h67 >> { n155, n75, n199 };
assign n285 = 4'h2 >> { n115, n138 };
assign n286 = 4'h8 >> { n188, n145 };
assign o_58_ = 64'hffffffff7fffffff >> { n169, n314, n255, n257, n288, n234 };
assign n288 = 4'h2 >> { o_15_, n214 };
assign n289 = 16'h1115 >> { n98, n185, n103, n92 };
assign o_60_ = 64'h7fffffffffffffff >> { n150, n257, n266, n278, n291, n237 };
assign n291 = 32'd8 >> { n184, o_7_, o_11_, n243, n274 };
assign o_61_ = 64'h7fffffffffffffff >> { n293, n150, n257, n285, n286, n294 };
assign n95 = 32'd8 >> { i_5_, i_4_, i_3_, i_6_, i_7_ };
assign n293 = 8'h08 >> { n93, n128, n130 };
assign n294 = 16'h0008 >> { n158, n207, n273, n289 };
assign o_62_ = 16'hff7f >> { i_3_, n275, i_1_, n314 };
assign n296 = 32'd3151691776 >> { n182, n186, i_0_, i_1_, i_2_ };
assign n297 = 64'h0222002202220222 >> { n80, i_2_, i_0_, n121, i_1_, n209 };
assign n298 = 64'h0001000100000001 >> { n186, n103, n155, n173, n76, n201 };
assign o_37_ = 64'hff7fff7f7f7fff7f >> { n92, n146, n97, n338, n215, n217 };
assign n300 = 64'h0000000080000000 >> { n80, n220, n221, n222, n223, n224 };
assign o_38_ = 64'hf7f7f7f7f7f777f7 >> { n95, i_5_, n161, n115, n127, n300 };
assign n302 = 64'h3737373737377737 >> { i_4_, i_5_, i_6_, i_3_, n101, n113 };
assign o_15_ = 4'h8 >> { n97, n98 };
assign n303 = 32'd32768 >> { i_2_, n302, n214, n218, n220 };
assign o_41_ = 8'h7f >> { n303, n232, n238 };
assign n305 = 64'h6e4c6e4c6e4c7f5d >> { n93, n103, i_6_, i_7_, i_5_, i_3_ };
assign n306 = 64'h0000000000008000 >> { i_4_, n158, n154, n205, n211, n249 };
assign o_42_ = 16'h7fff >> { n305, n306, n340, n241 };
assign n308 = 64'h0000153715371537 >> { n101, n121, n90, n95, n75, n113 };
assign n309 = 16'h4a5b >> { n240, n183, n184, n101 };
assign n310 = 64'h222222222222222a >> { n76, n92, i_4_, n117, n97, n227 };
assign o_43_ = 64'h7fffffffffffffff >> { n310, n131, n157, n241, n247, n340 };
assign n312 = 64'h880a0002aaaaaaaa >> { n78, i_5_, i_4_, i_6_, i_3_, n188 };
assign n97 = 8'h08 >> { i_0_, i_1_, i_2_ };
assign o_44_ = 32'd2147483647 >> { n312, n127, n168, n248, n314 };
assign n314 = 64'h2222000222222002 >> { n92, i_0_, i_2_, i_1_, n155, n178 };
assign n315 = 64'h111111111111111b >> { n92, n98, n113, n121, n78, n97 };
assign o_45_ = 64'hffffffffffff7fff >> { n75, n90, n315, n127, n159, n249 };
assign n317 = 64'ha8a8a8a8a8a8a8aa >> { i_2_, i_5_, i_4_, i_0_, i_1_, n192 };
assign n318 = 64'h0004040400555555 >> { n93, n101, n129, n121, n161, n117 };
assign n319 = 64'h8088808888888088 >> { n113, i_2_, i_0_, i_1_, n318, n274 };
assign n320 = 64'h7e76765c7e767e7e >> { i_4_, i_3_, i_0_, n92, i_2_, i_1_ };
assign o_53_ = 32'd2147483647 >> { n320, n176, n276, n277, n278 };
assign n322 = 64'h0000444544474447 >> { n97, n113, n166, n167, n90, n92 };
assign n98 = 32'd32768 >> { i_4_, i_5_, i_3_, i_6_, i_7_ };
assign n323 = 64'h0000000800800088 >> { n98, n78, n121, n97, n322, n203 };
assign o_55_ = 32'd2147483647 >> { n323, n176, n276, n277, n285 };
assign n325 = 64'h00000080050505c5 >> { n80, n76, n113, n97, n181, n98 };
assign n326 = 64'h0000000000008000 >> { n152, n169, n325, n206, n223, n284 };
assign o_56_ = 32'd2147483647 >> { n326, n127, n238, n248, n286 };
assign n328 = 64'hf700f7fff500f5fd >> { i_6_, n152, n76, i_2_, i_0_, i_1_ };
assign n329 = 64'h0000000000008000 >> { n92, o_19_, n195, n203, n228, n289 };
assign o_59_ = 32'd2147483647 >> { n328, n329, n189, n271, n319 };
assign n331 = 64'h0080008000800888 >> { n93, n103, n76, n161, n143, n165 };
assign n332 = 64'h0808080808080888 >> { n101, n97, n115, n113, n193, n195 };
assign o_10_ = 8'ha8 >> { n98, n92, n97 };
assign o_34_ = 32'd2147483647 >> { n331, n332, n189, n197, n202 };
assign n334 = 64'h797f7b7f7b7f7b7f >> { i_6_, i_7_, n78, i_3_, i_4_, i_5_ };
assign n335 = 64'h0008008800000080 >> { i_3_, n75, n210, n334, n188, n211 };
assign o_35_ = 16'h7fff >> { n335, n148, n160, n297 };
assign n337 = 64'h1b1f333f1b1a3333 >> { i_0_, i_4_, i_1_, i_2_, n200, i_3_ };
assign n338 = 64'h0000000080000000 >> { n113, n337, n153, n175, n178, n298 };
assign n339 = 64'hbbbbbff7bbbbff57 >> { i_7_, i_4_, i_5_, i_6_, n75, i_3_ };
assign n340 = 32'd128 >> { n166, n179, n339, n308, n309 };
assign n341 = 64'h0088088808880888 >> { n76, i_0_, i_1_, i_2_, n237, n264 };
assign o_50_ = 64'h7fffffffffffffff >> { n341, n153, n154, n177, n257, n317 };
assign o_11_ = 4'h8 >> { n92, n101 };
assign n343 = 64'h0000aa020002aa02 >> { n101, n80, n97, n129, n184, n282 };
assign n344 = 64'h0202020202020222 >> { n76, n113, n133, n101, n196, n267 };
assign o_54_ = 32'd4294934527 >> { n135, n344, n280, n283, n343 };
assign n346 = 64'h1111111111111115 >> { n76, i_4_, n113, n121, n97, n184 };
assign n347 = 64'h0000000000000080 >> { o_25_, n135, n171, n154, n190, n195 };
assign o_57_ = 32'd4294934527 >> { n115, n346, n347, n232, n280 };
assign n101 = 8'h08 >> { i_2_, i_1_, i_0_ };
assign o_12_ = 4'h8 >> { n103, n92 };
assign n76 = 16'h0002 >> { i_5_, i_4_, i_6_, i_3_ };
assign n103 = 8'h08 >> { i_1_, i_2_, i_0_ };
assign o_13_ = 4'h8 >> { n90, n98 };
assign o_14_ = 4'h8 >> { n78, n98 };
assign o_16_ = 4'h8 >> { n98, n101 };
assign o_17_ = 4'he >> { n108, n109 };
assign n108 = 64'h0000000000000080 >> { i_2_, i_1_, i_5_, i_0_, i_4_, i_3_ };
assign n109 = 64'h0000000000000008 >> { i_2_, i_1_, i_5_, i_3_, i_4_, i_0_ };
assign o_18_ = 64'h0000000000000080 >> { i_1_, i_0_, i_5_, i_2_, i_4_, i_3_ };
assign o_19_ = 32'd2 >> { i_2_, i_1_, i_0_, i_3_, i_4_ };
assign o_22_ = 8'ha8 >> { n113, n95, n78 };
assign o_21_ = 4'h8 >> { n76, n78 };
assign n113 = 32'd128 >> { i_5_, i_4_, i_3_, i_6_, i_7_ };
assign o_23_ = 8'h80 >> { n115, i_5_, i_3_ };
assign n115 = 8'h01 >> { i_2_, i_1_, i_0_ };
assign o_24_ = 4'h8 >> { n115, n117 };
assign n117 = 32'd2 >> { i_5_, i_4_, i_3_, i_7_, i_6_ };
assign o_25_ = 4'h8 >> { n90, n117 };
assign o_30_ = 4'h8 >> { n120, i_7_ };
assign n120 = 4'h8 >> { n93, n121 };
assign n121 = 16'h0002 >> { i_5_, i_4_, i_3_, i_6_ };
assign o_26_ = 8'h80 >> { n95, i_2_, i_0_ };
assign n78 = 8'h02 >> { i_2_, i_1_, i_0_ };
assign o_27_ = 4'h8 >> { n97, n117 };
assign o_28_ = 4'h8 >> { n103, n113 };
assign o_29_ = 8'h80 >> { n80, n115, i_7_ };
assign o_31_ = 64'hffffffffffff7fff >> { i_1_, n210, n139, n142, n127, n136 };
assign n127 = 16'h0008 >> { n93, n103, n130, n128 };
assign n128 = 64'h555555555577457f >> { i_4_, i_7_, i_3_, i_6_, i_5_, n93 };
assign n129 = 4'h8 >> { i_4_, i_3_ };
assign n130 = 32'd1430603077 >> { i_6_, i_7_, i_5_, i_4_, n101 };
assign n131 = 32'd353703231 >> { n133, n132, n80, n97, n90 };
assign n132 = 8'h80 >> { i_5_, i_4_, i_3_ };
assign o_20_ = 4'h8 >> { n78, n80 };
assign n133 = 32'd134744064 >> { i_7_, i_6_, i_4_, i_5_, i_3_ };
assign n134 = 8'h15 >> { n121, n97, n135 };
assign n135 = 64'h0000000000000080 >> { i_2_, i_0_, i_5_, i_1_, i_4_, i_3_ };
assign n136 = 8'h02 >> { n113, n137, n138 };
assign n137 = 8'ha8 >> { n133, n129, n115 };
assign n138 = 4'hd >> { i_3_, n75 };
assign n139 = 4'h2 >> { o_17_, n141 };
assign n140 = 32'd4194040827 >> { i_6_, i_7_, i_3_, i_4_, i_5_ };
assign n141 = 32'd2880175035 >> { n78, i_7_, i_6_, i_5_, i_4_ };
assign n142 = 8'h80 >> { n143, n144, n145 };
assign n80 = 16'h0001 >> { i_5_, i_4_, i_3_, i_6_ };
assign n143 = 16'hfddd >> { i_5_, i_4_, i_3_, n115 };
assign n144 = 8'hd5 >> { i_6_, i_3_, n90 };
assign n145 = 16'h9f1f >> { i_5_, n75, i_3_, i_4_ };
assign n146 = 32'd4294966655 >> { i_4_, i_5_, i_6_, i_7_, i_3_ };
assign o_32_ = 32'd2147483647 >> { n139, n148, n150, n156, n162 };
assign n148 = 32'd8 >> { n149, n93, n103, n130, n128 };
assign n149 = 8'ha8 >> { n113, n86, n115 };
assign n150 = 16'h0080 >> { n97, n151, n154, n153 };
assign n151 = 16'h1115 >> { n76, n113, n90, n152 };
assign n152 = 32'd8 >> { i_2_, i_0_, i_3_, i_4_, i_1_ };
assign o_0_ = 4'he >> { n76, n80 };
assign n153 = 16'hfddd >> { i_4_, i_5_, i_3_, n78 };
assign n154 = 64'h00011111000fffff >> { n90, n97, n80, n117, n129, n98 };
assign n155 = 32'd128 >> { i_0_, i_3_, i_2_, i_4_, i_1_ };
assign n156 = 16'h0008 >> { o_7_, n98, n157, n159 };
assign n157 = 16'h1115 >> { n80, n95, n115, n158 };
assign n158 = 64'h0000000000000002 >> { i_2_, i_0_, i_5_, i_4_, i_3_, i_1_ };
assign n159 = 16'h555d >> { i_4_, i_5_, i_6_, n115 };
assign n160 = 32'd221196079 >> { n75, n80, n115, o_5_, n161 };
assign n161 = 32'd1467447159 >> { i_7_, i_5_, i_6_, i_4_, i_3_ };
assign n162 = 16'hddd5 >> { i_4_, i_5_, i_3_, n75 };
assign o_1_ = 4'h2 >> { i_5_, n83 };
assign o_33_ = 64'h7fffffffffffffff >> { n164, n168, n174, n176, n296, n187 };
assign n164 = 4'h2 >> { n167, n165 };
assign n165 = 4'h1 >> { o_4_, n166 };
assign n166 = 64'h0000000000008000 >> { i_5_, i_4_, i_0_, i_2_, i_1_, i_3_ };
assign n167 = 16'h8000 >> { i_2_, i_1_, i_0_, i_4_ };
assign n168 = 16'h0008 >> { n169, n97, n172, n170 };
assign n169 = 4'h2 >> { n161, n115 };
assign n170 = 16'h1101 >> { n140, n90, n171, n158 };
assign n171 = 32'd128 >> { i_1_, i_0_, i_2_, i_4_, i_3_ };
assign n172 = 8'h57 >> { n76, n113, n115 };
endmodule

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@ -0,0 +1,361 @@
a 0.502800 0.496400
b 0.501400 0.493200
c 0.506200 0.497000
d 0.499200 0.503000
e 0.496000 0.508600
f 0.506200 0.506200
g 0.499600 0.496600
h 0.504200 0.502800
i 0.505800 0.505200
j 0.503800 0.504400
k 0.493000 0.505000
l 0.488000 0.500400
m 0.483600 0.503800
n 0.494800 0.508200
n31 0.971200 0.012381
n32 0.169200 0.254799
n33 0.241800 0.101468
n34 0.318600 0.019369
n35 0.144800 0.002069
n36 0.976600 0.000000
n37 0.007400 0.000121
n38 0.747600 0.063099
n39 0.237400 0.096630
n40 0.257600 0.093704
n41 0.007200 0.000115
n42 0.873400 0.015624
n43 0.173800 0.016270
n44 0.077600 0.000493
n45 0.122000 0.025969
n46 0.242800 0.093962
n47 0.871000 0.035631
n48 0.263400 0.098041
n49 0.130000 0.027551
n50 0.936800 0.030205
n51 0.016200 0.005376
n52 0.255200 0.092533
n53 0.239600 0.092126
n54 0.940400 0.042919
n55 0.024600 0.000640
n56 0.990000 0.012290
n57 0.006200 0.001459
n58 0.152800 0.002069
n59 0.017600 0.000499
n60 0.932600 0.041320
n61 0.936400 0.004186
n62 0.004600 0.000033
n63 0.252600 0.095459
n64 0.003400 0.001409
n65 0.969800 0.038111
n66 0.129400 0.027627
n67 0.130600 0.028418
n68 0.118400 0.026917
n69 0.007600 0.000917
n70 0.951000 0.292869
n71 0.247000 0.092709
n72 0.061400 0.007508
n73 0.085000 0.001583
n74 0.763200 0.044446
n75 0.236200 0.085383
n76 0.028400 0.002040
n77 0.981000 0.153923
n78 0.007400 0.000116
n79 0.120000 0.027018
n80 0.031000 0.001876
n81 0.857400 0.028378
n82 0.122600 0.026334
n83 0.982800 0.000268
n84 0.247200 0.091138
n85 0.133200 0.027985
n86 0.011200 0.024585
n87 0.789400 0.031612
n88 0.047200 0.033737
n89 0.967800 0.000865
n90 0.972400 0.000078
n91 0.060400 0.007378
n92 0.246200 0.091356
n93 0.007800 0.001285
n94 0.127400 0.027437
t2 0.081600 0.231317
n96 0.957400 0.024120
n97 0.976400 0.000852
n98 0.121200 0.026674
n99 0.243600 0.095990
n100 0.122400 0.026464
n101 0.013000 0.000222
n102 0.009600 0.000161
n103 0.020600 0.000586
n104 0.004600 0.000074
n105 0.798400 0.056722
n106 0.806400 0.026376
n107 0.286600 0.035213
n108 0.536000 0.047443
n109 0.030400 0.001890
n110 0.897200 0.000053
n111 0.017200 0.000478
n112 0.014000 0.000490
n113 0.256800 0.095334
n114 0.259200 0.095642
n115 0.007000 0.187214
n116 0.044200 0.050038
n117 0.254400 0.101846
n118 0.126200 0.027160
n119 0.010600 0.034212
n120 0.815400 0.030997
n121 0.967800 0.000923
n122 0.929200 0.000153
n123 0.990800 0.000071
n124 0.985000 0.000006
n125 0.003400 0.000009
n126 0.996200 0.000000
n127 0.006200 0.000067
n128 0.016800 0.000644
n129 0.025800 0.000531
n130 0.990600 0.000000
n131 0.954000 0.002745
n132 0.000400 0.000001
n133 0.059600 0.007598
n134 0.000800 0.000002
n135 0.000200 0.000001
n136 0.248200 0.091356
n137 0.129800 0.031039
n138 0.009600 0.001467
n139 0.991200 0.000006
n140 0.124600 0.184237
n141 0.893200 0.130895
n142 0.714800 0.035578
n143 0.942200 0.010487
n144 0.253000 0.101468
n145 0.005800 0.000039
n146 0.128200 0.027579
n147 0.997400 0.000000
n148 0.001200 0.000002
n149 0.003800 0.004767
n150 0.056000 0.007244
n151 0.976800 0.000000
n152 0.883400 0.009123
n153 0.249000 0.094900
n154 0.706600 0.020911
n155 0.009400 0.000192
n156 0.847000 0.026708
n157 0.535400 0.045916
n158 0.007200 0.000042
n159 0.642800 0.041109
n160 0.036000 0.001858
n161 0.249200 0.093349
n162 0.974800 0.000005
n163 0.014600 0.001499
n164 0.944800 0.084937
n165 0.919600 0.021938
n166 0.009000 0.000397
n167 0.025400 0.000909
n168 0.015000 0.000232
n169 0.986200 0.000001
n170 0.943000 0.000001
n171 0.029000 0.001933
n172 0.024200 0.250774
n173 0.012800 0.002989
n174 0.978600 0.000129
n175 0.007800 0.225668
n176 0.013600 0.000464
n177 0.033000 0.000605
n178 0.006400 0.000054
n179 0.006800 0.000591
n180 0.954800 0.002247
n181 0.001600 0.027734
n182 0.973000 0.023736
n183 0.003200 0.000033
n184 0.532600 0.047090
n185 0.004000 0.000032
n186 0.000600 0.000002
n187 0.000000 0.000000
n188 0.122400 0.027262
n189 0.125800 0.027184
n190 0.998200 0.004868
n191 0.001200 0.033473
n192 0.014200 0.000518
n193 0.248600 0.093739
n194 0.118000 0.026073
n195 0.000200 0.000000
n196 0.016200 0.000509
n197 0.000200 0.001820
n198 0.008400 0.000137
n199 0.016600 0.000533
n200 0.247800 0.091574
n201 0.000000 0.000002
n202 0.019600 0.000497
n203 0.133600 0.029869
n204 0.017600 0.000490
n205 0.997200 0.000000
n206 0.999400 0.097558
n207 0.059200 0.006543
n208 0.014600 0.004075
n209 0.120000 0.026449
n210 0.019000 0.000510
n211 0.000400 0.000040
n212 0.020200 0.003966
n213 0.126000 0.182202
n214 0.000200 0.000001
n215 0.123200 0.028549
n216 1.000000 0.000000
n217 0.014400 0.000483
n218 0.001600 0.000017
n219 0.000200 0.000005
n220 0.126800 0.027210
n221 0.007200 0.000107
n222 0.002400 0.000384
n223 0.007400 0.007061
j2 0.001800 0.003589
n225 0.127400 0.031214
n226 0.016200 0.000484
n227 0.000400 0.000000
n228 0.000600 0.000020
n229 0.250200 0.090974
k2 0.002800 0.000010
n231 0.015600 0.000441
n232 0.017600 0.000504
n233 0.000200 0.000006
n234 0.015600 0.003952
n235 0.125600 0.026582
n236 0.998800 0.000000
n237 0.046800 0.048249
n238 0.043400 0.000688
n239 0.047200 0.000487
n240 0.011000 0.085944
n241 0.012600 0.000865
n242 0.955400 0.002422
n243 0.476600 0.143086
n244 0.921200 0.115516
n245 0.067600 0.007693
n246 0.782400 0.019507
n247 0.724400 0.091680
n248 0.008800 0.002944
n249 0.047200 0.016842
n250 0.021800 0.000000
n251 0.041800 0.000463
n252 0.072200 0.017522
n253 0.686200 0.034142
n254 0.019000 0.000507
n255 0.859400 0.026096
n256 0.017600 0.000544
n257 0.734400 0.092213
n258 0.031800 0.001005
n259 0.017600 0.000548
n260 0.017200 0.000525
n261 0.982000 0.000220
n262 0.015000 0.000524
n263 0.062000 0.007913
n264 0.479800 0.003717
n265 0.015600 0.000492
n266 0.110400 0.009275
n267 0.443200 0.262740
n268 0.459600 0.002069
n269 0.782400 0.012675
n270 0.687800 0.000275
n271 0.065000 0.003821
n272 0.095600 0.000030
n273 0.018000 0.000509
n274 0.765800 0.007392
n275 0.739000 0.090277
n276 0.831400 0.029543
n277 0.730600 0.146757
n278 0.016200 0.000514
n279 0.942600 0.000529
n280 0.040600 0.005534
n281 0.857800 0.016045
n282 0.039200 0.051252
n283 0.712200 0.156053
n284 0.016400 0.000519
n285 0.932000 0.008084
n286 0.036600 0.000922
n287 0.030200 0.002443
n288 0.956000 0.000000
n289 0.014800 0.000505
n290 0.994400 0.028439
n291 0.949800 0.035851
n292 0.979200 0.000000
r2 0.095800 0.163284
n294 0.966000 0.000696
s2 0.093000 0.163132
n296 0.328800 0.029274
n297 0.941200 0.021840
n298 0.926800 0.005148
n299 0.965200 0.000942
u2 0.088200 0.120903
n301 0.033000 0.003773
n302 0.992200 0.000000
n303 0.890400 0.004814
n304 0.980200 0.014265
p2 0.089200 0.006588
n306 0.980000 0.000385
q2 0.090600 0.086017
n308 0.981000 0.000206
n309 0.937400 0.000317
n310 0.077000 0.084571
n311 0.193000 0.022498
n312 0.998400 0.000002
n313 0.980800 0.000004
n314 0.040400 0.001267
h2 0.030600 0.000000
n316 0.007800 0.000006
n317 0.994800 0.000000
n318 0.993800 0.010322
n319 0.985000 0.000112
i2 0.056600 0.000069
n321 0.977400 0.038437
n322 0.975800 0.000052
n323 0.085400 0.002206
n324 0.007400 0.005761
n325 0.997800 0.000007
n326 0.006400 0.000041
n327 1.000000 0.000000
n328 0.014000 0.000483
n329 0.020000 0.087180
n330 0.999000 0.000000
n331 0.011800 0.000147
n332 0.002200 0.000008
n333 0.997800 0.001996
n334 0.000200 0.000005
n335 0.999800 0.092126
m2 0.003600 0.007551
n337 0.039800 0.019880
n338 0.866600 0.000460
n339 0.986200 0.247511
n340 0.988600 0.000161
n341 0.800600 0.019765
n342 0.468800 0.058180
n343 0.403400 0.018596
n344 0.943600 0.012928
n345 0.927800 0.054930
n346 0.246800 0.015623
n347 0.902200 0.011659
n348 0.233200 0.264304
n349 0.324800 0.145340
n350 0.349200 0.016970
n351 0.973400 0.092742
n352 0.673200 0.011045
n353 0.757200 0.000693
n354 0.178600 0.035918
n355 0.091200 0.000020
n356 0.502600 0.206034
n357 0.930600 0.000033
n358 0.830800 0.000594
n359 0.218400 0.095701
n360 0.958800 0.001136
n361 0.084800 0.072778
n362 0.052600 0.023139
n363 0.946800 0.000004
n2 0.093400 0.087406
n365 0.405200 0.020623
n366 0.987600 0.000181
n367 0.070400 0.003716
o2 0.092600 0.153987
n369 0.000800 0.000058
n370 0.999400 0.000000
n371 0.974400 0.000190
n372 0.567000 0.030023
n373 0.875200 0.000008
n374 0.816800 0.085360
n375 0.888400 0.037555
n376 0.851600 0.017052
l2 0.573800 0.145584

1064
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@ -0,0 +1,712 @@
/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
module misex3(a, b, c, d, e, f, g, h, i, j, k, l, m, n, r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2);
input a;
input b;
input c;
input d;
input e;
input f;
input g;
input h;
output h2;
input i;
output i2;
input j;
output j2;
input k;
output k2;
input l;
output l2;
input m;
output m2;
input n;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n147;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n163;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
output n2;
wire n200;
wire n201;
wire n202;
wire n203;
wire n204;
wire n205;
wire n206;
wire n207;
wire n208;
wire n209;
wire n210;
wire n211;
wire n212;
wire n213;
wire n214;
wire n215;
wire n216;
wire n217;
wire n218;
wire n219;
wire n220;
wire n221;
wire n222;
wire n223;
wire n225;
wire n226;
wire n227;
wire n228;
wire n229;
wire n231;
wire n232;
wire n233;
wire n234;
wire n235;
wire n236;
wire n237;
wire n238;
wire n239;
wire n240;
wire n241;
wire n242;
wire n243;
wire n244;
wire n245;
wire n246;
wire n247;
wire n248;
wire n249;
wire n250;
wire n251;
wire n252;
wire n253;
wire n254;
wire n255;
wire n256;
wire n257;
wire n258;
wire n259;
wire n260;
wire n261;
wire n262;
wire n263;
wire n264;
wire n265;
wire n266;
wire n267;
wire n268;
wire n269;
wire n270;
wire n271;
wire n272;
wire n273;
wire n274;
wire n275;
wire n276;
wire n277;
wire n278;
wire n279;
wire n280;
wire n281;
wire n282;
wire n283;
wire n284;
wire n285;
wire n286;
wire n287;
wire n288;
wire n289;
wire n290;
wire n291;
wire n292;
wire n294;
wire n296;
wire n297;
wire n298;
wire n299;
wire n301;
wire n302;
wire n303;
wire n304;
wire n306;
wire n308;
wire n309;
wire n31;
wire n310;
wire n311;
wire n312;
wire n313;
wire n314;
wire n316;
wire n317;
wire n318;
wire n319;
wire n32;
wire n321;
wire n322;
wire n323;
wire n324;
wire n325;
wire n326;
wire n327;
wire n328;
wire n329;
wire n33;
wire n330;
wire n331;
wire n332;
wire n333;
wire n334;
wire n335;
wire n337;
wire n338;
wire n339;
wire n34;
wire n340;
wire n341;
wire n342;
wire n343;
wire n344;
wire n345;
wire n346;
wire n347;
wire n348;
wire n349;
wire n35;
wire n350;
wire n351;
wire n352;
wire n353;
wire n354;
wire n355;
wire n356;
wire n357;
wire n358;
wire n359;
wire n36;
wire n360;
wire n361;
wire n362;
wire n363;
wire n365;
wire n366;
wire n367;
wire n369;
wire n37;
wire n370;
wire n371;
wire n372;
wire n373;
wire n374;
wire n375;
wire n376;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n96;
wire n97;
wire n98;
wire n99;
output o2;
output p2;
output q2;
output r2;
output s2;
output t2;
output u2;
assign n31 = 64'hf5fdf7fff7fff7ff >> { n35, h, n32, d, g, e };
assign n40 = 4'h8 >> { d, b };
assign n130 = 32'd16843008 >> { n120, n131, n134, n135, n132 };
assign n131 = 64'hf7ff7f7f77ff7fff >> { l, h, k, g, n33, i };
assign n132 = 16'h8000 >> { n84, n75, n71, n133 };
assign n133 = 16'h0008 >> { n, d, c, a };
assign n134 = 32'd32768 >> { l, n109, n33, i, k };
assign n135 = 32'd2147483648 >> { n136, n66, n99, n137, c };
assign n136 = 4'h2 >> { j, i };
assign n137 = 8'h02 >> { m, n, l };
assign n138 = 32'd572530720 >> { n92, l, n84, n105, n79 };
assign n139 = 16'h2202 >> { n108, n78, n125, n126 };
assign n41 = 8'h08 >> { n42, n45, c };
assign n140 = 4'h2 >> { l, n33 };
assign n141 = 8'ha2 >> { n142, n52, n143 };
assign n142 = 32'd1465350135 >> { c, d, e, f, b };
assign n143 = 32'd4160749439 >> { f, d, e, h, b };
assign n144 = 4'h2 >> { m, n };
assign n145 = 64'h0000088000000800 >> { n32, n120, n140, j, k, g };
assign n146 = 8'h08 >> { h, i, g };
assign n147 = 64'h5555555555551555 >> { n120, h, g, i, n91, n148 };
assign n148 = 32'd128 >> { l, j, n33, n109, k };
assign n149 = 64'h0008000808080008 >> { n120, g, n105, i, h, n150 };
assign n42 = 8'h27 >> { n44, n43, h };
assign n150 = 16'h0008 >> { j, n, m, l };
assign n151 = 64'h1111111111110111 >> { n152, m, i, n113, n158, n155 };
assign n152 = 16'hdd0d >> { n154, n153, n141, n };
assign n153 = 4'h8 >> { h, g };
assign n154 = 64'hfd75727f7d75727f >> { f, c, d, e, b, n };
assign n155 = 16'h0080 >> { n156, n113, i, h };
assign n156 = 64'hfefefefedcfefefe >> { b, f, c, n157, m, n };
assign n157 = 32'd2503415095 >> { g, e, d, f, c };
assign n158 = 64'ha0a8a0a8a8a8a0a8 >> { f, n107, n159, n109, g, n160 };
assign n159 = 64'ha7a777b7272f553f >> { c, e, d, b, f, a };
assign n43 = 64'h02080a080a080a08 >> { i, l, j, m, k, n };
assign n160 = 32'd128 >> { n, k, j, m, h };
assign n161 = 4'h8 >> { k, h };
assign n162 = 8'h45 >> { n79, n110, n163 };
assign n163 = 32'd134785544 >> { n154, n146, n164, n, n117 };
assign n164 = 64'h3133313331331111 >> { g, n142, n68, f, n59, n84 };
assign n165 = 32'd3445485439 >> { n150, j, n33, i, k };
assign n166 = 32'd1431589972 >> { n76, j, n168, n167, n120 };
assign n167 = 8'h08 >> { n, n73, g };
assign n168 = 32'd2290092032 >> { j, l, k, n146, n33 };
assign n169 = 32'd1414813012 >> { n109, n106, h, n170, n158 };
assign n44 = 64'h0800080008080800 >> { j, l, k, m, n, i };
assign n170 = 32'd1431639381 >> { k, n33, l, i, n171 };
assign n171 = 32'd32768 >> { n, i, m, j, k };
assign n172 = 64'h00fd00ff00fd00fd >> { n72, n106, n, n175, n173, n174 };
assign n173 = 64'h0808080888080808 >> { n120, n136, g, n110, k, n75 };
assign n174 = 64'hffffdff7fff7dff7 >> { n110, n120, g, j, h, n75 };
assign n175 = 4'h2 >> { n157, n176 };
assign n176 = 64'h0000000000008000 >> { i, m, l, j, k, h };
assign n177 = 64'h02080a0200080800 >> { i, j, k, n156, h, l };
assign n178 = 64'h0000800800008000 >> { h, n120, n113, g, n33, l };
assign n179 = 64'h0080008000000080 >> { n109, n106, h, l, j, n33 };
assign n45 = 4'h8 >> { n46, b };
assign n180 = 32'd4160223061 >> { n142, g, f, n68, n84 };
assign n181 = 16'h0080 >> { b, f, c, n176 };
assign n182 = 64'h0f0d0f0d0d0d0f0d >> { n184, n153, n141, n183, i, n144 };
assign n183 = 64'h0000000000000080 >> { i, c, e, n48, n153, d };
assign n184 = 32'd3012899733 >> { f, e, d, b, c };
assign n185 = 32'd32768 >> { n50, c, d, b, a };
assign n186 = 16'h0080 >> { j, n109, n79, i };
assign n187 = 16'h8000 >> { n67, n137, n188, n189 };
assign n188 = 8'h02 >> { c, d, e };
assign n189 = 8'h02 >> { j, k, i };
assign n46 = 4'h2 >> { f, e };
assign n190 = 16'h2227 >> { n191, n195, n125, n94 };
assign n191 = 64'h8080808088808080 >> { g, n114, n193, n192, n194, n48 };
assign n192 = 64'h0000000080000000 >> { g, j, i, k, h, l };
assign n193 = 4'h1 >> { i, h };
assign n194 = 8'h01 >> { f, c, d };
assign n195 = 8'h80 >> { n66, n188, n196 };
assign n196 = 64'h0000000000000080 >> { i, m, n, j, l, k };
assign n197 = 32'd8 >> { f, g, e, n200, n198 };
assign n198 = 4'h8 >> { n199, h };
assign n199 = 64'h0000000000008000 >> { m, n, i, l, j, k };
assign n47 = 64'h92135757ffffffff >> { n48, i, l, j, k, h };
assign n200 = 4'h1 >> { c, d };
assign n201 = 32'd128 >> { m, h, n202, n114, n92 };
assign n202 = 64'h8000000000000000 >> { f, g, c, e, d, b };
assign n203 = 8'h01 >> { l, m, n };
assign n204 = 64'h0000000080000000 >> { h, f, g, c, e, d };
assign n205 = 64'h0000000000000008 >> { n211, n214, n218, n219, n206, n216 };
assign n206 = 16'h7d7f >> { n208, n209, n207, n210 };
assign n207 = 8'h80 >> { n53, n, e };
assign n208 = 8'h08 >> { h, n100, n53 };
assign n209 = 8'h08 >> { b, d, c };
assign n48 = 4'h1 >> { m, n };
assign n210 = 64'h0000000000000080 >> { i, m, h, j, k, l };
assign n211 = 16'h0008 >> { e, d, n212, n213 };
assign n212 = 32'd2 >> { k, f, g, c, n48 };
assign n213 = 4'h2 >> { l, n193 };
assign n214 = 64'h0000000080000000 >> { f, n48, n215, n189, l, n153 };
assign n215 = 8'h08 >> { e, c, d };
assign n216 = 32'd2139062271 >> { n196, n217, n53, n210, n215 };
assign n217 = 64'h0000000000008000 >> { f, e, c, g, d, b };
assign n218 = 16'h8000 >> { n43, n52, n85, e };
assign n219 = 32'd128 >> { m, k, l, n217, n220 };
assign n49 = 8'h80 >> { c, e, d };
assign n220 = 8'h08 >> { j, i, h };
assign n221 = 16'h0008 >> { n54, c, b, a };
assign n222 = 16'h0080 >> { g, n84, n85, n58 };
assign n223 = 16'h22a2 >> { n42, n63, n61, n209 };
assign j2 = 16'hfff7 >> { n197, n228, n330, n327 };
assign n225 = 8'h02 >> { m, k, l };
assign n226 = 64'h0000000000008000 >> { e, a, f, d, b, c };
assign n227 = 64'h8000000000000000 >> { n53, n225, n209, n220, n, e };
assign n228 = 32'd32768 >> { g, n193, n194, n229, n203 };
assign n229 = 4'h1 >> { j, k };
assign n32 = 4'h2 >> { n34, n33 };
assign n50 = 8'h15 >> { n53, n32, n51 };
assign k2 = 64'hddddddddddddfddd >> { f, g, n198, n188, n211, n333 };
assign n231 = 64'h8000000000000000 >> { l, j, i, m, k, h };
assign n232 = 64'h8000000000000000 >> { f, c, e, d, b, a };
assign n233 = 64'h0000000000008000 >> { i, f, n137, n229, n52, n215 };
assign n234 = 32'd2 >> { j, i, f, e, n52 };
assign n235 = 8'h02 >> { f, e, c };
assign n236 = 64'h1111111101111111 >> { i, n203, n204, n113, n201, n191 };
assign n237 = 32'd2863311522 >> { n238, n240, n241, n242, g };
assign n238 = 64'h00ffffff00808080 >> { n239, c, b, h, n171, l };
assign n239 = 64'h0001000000010001 >> { c, n, i, h, m, e };
assign n51 = 8'h08 >> { f, n35, n52 };
assign n240 = 64'h3120202020202020 >> { i, n48, n113, n199, d, h };
assign n241 = 32'd134742024 >> { a, n85, k, n220, n33 };
assign n242 = 64'hfff7fff7fff7fdf5 >> { i, f, e, m, n, n200 };
assign n243 = 64'h1113131313131313 >> { n84, n113, b, n213, f, n144 };
assign n244 = 32'd353703253 >> { d, a, n193, n150, n245 };
assign n245 = 64'h0222020200220002 >> { b, d, c, e, g, n144 };
assign n246 = 64'hfffabffafffa9dd8 >> { i, e, c, b, a, d };
assign n247 = 64'hbbbfbbbb9b9f9b9b >> { j, b, k, l, n, m };
assign n248 = 64'h0000008000080088 >> { c, b, m, n, n161, n118 };
assign n249 = 32'd134752776 >> { k, n220, g, n200, n48 };
assign n52 = 4'h2 >> { g, h };
assign n250 = 32'd1145328708 >> { n, n231, g, n251, a };
assign n251 = 64'h0008000000080008 >> { h, k, n, e, m, d };
assign n252 = 64'h080a000200020002 >> { n49, f, h, j, i, g };
assign n253 = 32'd368918013 >> { k, g, h, j, i };
assign n254 = 8'h80 >> { n63, n113, n84 };
assign n255 = 32'd4278120190 >> { d, n136, g, c, f };
assign n256 = 16'h8000 >> { n49, i, f, g };
assign n257 = 64'h7decfdecfdecfdec >> { c, b, f, a, e, d };
assign n258 = 64'h0000000000000028 >> { j, m, k, i, g, h };
assign n259 = 64'h0000000000000008 >> { l, j, m, k, i, h };
assign n53 = 4'h2 >> { f, g };
assign n260 = 64'h0000000000000080 >> { m, k, h, i, j, f };
assign n261 = 64'h00ff007f007f007f >> { d, e, n262, g, n231, f };
assign n262 = 64'h0000000000000008 >> { j, m, k, g, f, h };
assign n263 = 16'h0002 >> { n, f, e, m };
assign n264 = 32'd572654114 >> { i, n200, n48, n265, h };
assign n265 = 32'd32768 >> { m, n229, n, e, b };
assign n266 = 64'h0444044455550444 >> { k, n150, d, c, n144, i };
assign n267 = 32'd2863311402 >> { i, d, c, n48, n268 };
assign n268 = 32'd1431655761 >> { l, n, k, i, h };
assign n269 = 64'hfffdfff0bbb9fff0 >> { k, g, f, b, j, e };
assign n54 = 64'hdd5dff7fff7fff7f >> { n35, h, n34, n33, g, f };
assign n270 = 64'h5555401155554051 >> { n46, m, n, d, c, n271 };
assign n271 = 64'h000000080002000a >> { c, b, m, e, n, i };
assign n272 = 32'd1145328708 >> { i, n48, c, n79, h };
assign n273 = 32'd128 >> { e, a, n113, d, g };
assign n274 = 32'd3149642507 >> { h, g, f, n229, l };
assign n275 = 32'd4008619758 >> { c, d, n46, a, b };
assign n276 = 64'h2031313131313131 >> { n193, n46, l, n277, n278, j };
assign n277 = 64'hfffaeeeaeeeaeeea >> { a, d, h, g, e, f };
assign n278 = 64'h0000000000008000 >> { j, k, i, h, g, e };
assign n279 = 8'h01 >> { n258, n259, n260 };
assign n55 = 32'd526344 >> { d, e, n47, c, f };
assign n280 = 64'h000800020008000a >> { j, i, m, b, k, n46 };
assign n281 = 32'd2004317959 >> { h, e, f, n49, n67 };
assign n282 = 64'haa08aa00aa08aa08 >> { d, n193, n235, c, g, n203 };
assign n283 = 64'hf3a2f3a2a2a2f3a2 >> { d, n46, c, j, n202, b };
assign n284 = 64'h0000000000000002 >> { j, m, n, c, d, k };
assign n285 = 64'hffbbdf9bdf9bdf9b >> { k, l, n277, n202, m, n };
assign n286 = 64'ha8a8a8a0a8a0a8a0 >> { n200, g, n235, n204, j, n48 };
assign n287 = 64'h0002000200000002 >> { k, n39, f, g, b, n144 };
assign n288 = 32'd1427457285 >> { a, b, n263, c, n289 };
assign n289 = 64'h0000000000000080 >> { j, m, k, n, h, f };
assign n56 = 8'h15 >> { n59, n58, n57 };
assign n290 = 64'h07f7f7f707777777 >> { k, n63, n199, h, n33, n232 };
assign n291 = 64'h3131313131311131 >> { e, n60, f, n31, n55, b };
assign n292 = 64'h0202020202000202 >> { n61, n40, c, n62, n64, n56 };
assign r2 = 16'hff7f >> { n69, n292, n36, n291 };
assign n294 = 64'hd5d5d5d580d5d5d5 >> { n47, d, f, n83, n56, c };
assign s2 = 64'hffffffffffffff7f >> { n69, n86, n93, n77, n36, n294 };
assign n296 = 64'h4c44dc5ca800a808 >> { h, j, i, l, k, g };
assign n297 = 32'd2934894318 >> { m, e, n296, n70, n };
assign n298 = 64'hf7a2f7f7ffa2fff7 >> { n109, l, n106, k, j, h };
assign n299 = 64'hf7f7f7f7f7f7f777 >> { n110, n113, n114, n298, m, i };
assign n57 = 32'd32768 >> { e, n40, h, f, n43 };
assign u2 = 32'd2004318039 >> { n115, n119, n299, n, n122 };
assign n301 = 64'h020f0202222f2222 >> { i, n140, n106, j, n141, n144 };
assign n302 = 64'hbbbbbbbbabbbbbbb >> { j, h, n33, k, n76, n120 };
assign n303 = 64'hff87ff87ff878880 >> { m, n152, n156, h, i, k };
assign n304 = 64'h4444ccc4ccc4ccc4 >> { n71, n133, n, n106, n169, n73 };
assign p2 = 32'd3724410365 >> { n303, n162, j, n166, n304 };
assign n306 = 64'hdddddddddddd0ddd >> { n105, j, i, n79, n182, k };
assign q2 = 64'hfffdfffdfdfdfffd >> { n163, n306, l, n149, n172, n309 };
assign n308 = 64'hfffffdf7fdfdfdf5 >> { n180, n141, k, m, j, l };
assign n309 = 64'h0002000202020002 >> { n181, n308, n, n179, n177, n313 };
assign n58 = 32'd538976800 >> { j, l, k, m, n };
assign n310 = 32'd2147516930 >> { n154, n71, n133, m, l };
assign n311 = 64'h2725252526202020 >> { n146, h, g, n133, k, j };
assign n312 = 16'hff7f >> { n133, n59, n39, n144 };
assign n313 = 16'h0222 >> { n311, n310, n178, n312 };
assign n314 = 64'h020666660a066e66 >> { e, n297, d, n54, b, a };
assign h2 = 64'hfbbbfbbbfffffbbb >> { n190, n54, c, n314, n318, n185 };
assign n316 = 64'h2020202022202020 >> { g, h, n150, n76, d, a };
assign n317 = 64'h0001000000010001 >> { n133, n70, n134, n148, n186, n187 };
assign n318 = 32'd35791394 >> { e, c, n316, n132, n317 };
assign n319 = 64'hdfdfdfdfdfdf55df >> { c, n42, g, f, n60, n40 };
assign n59 = 64'h0000000000008000 >> { h, e, f, i, d, b };
assign i2 = 32'd2147483647 >> { n319, n371, n205, n322, n318 };
assign n321 = 64'h0a0f2a2f2a2f2a2f >> { n53, n32, n82, n94, n51, n54 };
assign n322 = 64'h0101010101011101 >> { n104, n222, n321, e, n221, n324 };
assign n323 = 64'h0220222202002222 >> { n75, n87, h, n74, f, g };
assign n324 = 32'd2155907200 >> { n, n323, n51, a, n99 };
assign n325 = 64'hffffffffffff7fff >> { m, h, n, e, n53, n209 };
assign n326 = 64'hffd5d5d5d5d5d5d5 >> { n52, n33, n226, n48, n208, n325 };
assign n327 = 64'haaaaaaaa2aaaaaaa >> { k, i, n326, j, l, n216 };
assign n328 = 64'h0000000000008000 >> { j, k, i, l, h, g };
assign n329 = 64'h08080808ff080808 >> { f, n100, n48, n, m, n226 };
assign n33 = 4'h2 >> { n, m };
assign n60 = 32'd3470778335 >> { n58, i, n43, g, h };
assign n330 = 64'h0000000100010001 >> { n329, n328, n195, n214, n219, n227 };
assign n331 = 64'h8808800080008000 >> { f, n49, n232, m, k, g };
assign n332 = 64'h8888008000800080 >> { n117, n202, n, n331, i, h };
assign n333 = 32'd143165576 >> { n332, j, l, n206, n330 };
assign n334 = 64'h0000000080000000 >> { a, g, n39, n79, n193, n235 };
assign n335 = 64'h9dbfbfbfbfbfbfbf >> { c, n225, n234, n334, b, d };
assign m2 = 64'hffffffffffff7fff >> { n187, n233, n335, n236, n327, n333 };
assign n337 = 64'h22222222a2222222 >> { n114, n49, g, f, n281, n48 };
assign n338 = 64'h0404000455550055 >> { n144, i, n337, n192, n283, n282 };
assign n339 = 64'h7777777757777777 >> { h, n48, n113, i, n198, c };
assign n61 = 16'h5d7f >> { n44, n43, h, f };
assign n340 = 64'hffffff7ffff7ff77 >> { n92, n229, e, h, n144, n85 };
assign n341 = 64'h5444444444444444 >> { n340, n243, n244, n339, n343, n237 };
assign n342 = 64'hf0b0f0b0d090f0b0 >> { g, n188, n246, f, m, n };
assign n343 = 64'h0002000200000002 >> { n247, n193, n248, n249, n250, n342 };
assign n344 = 64'heeeeffefffefffef >> { g, n200, h, n53, k, i };
assign n345 = 64'hffaafeaafeaafeaa >> { h, j, n344, n114, n255, m };
assign n346 = 64'h1612171204001510 >> { e, g, d, h, f, c };
assign n347 = 64'hfefefefe54fefefe >> { b, n46, n144, n270, k, j };
assign n348 = 64'h07070f070f070f07 >> { a, d, n263, n350, n264, n347 };
assign n349 = 64'h7272fa72fa72fa72 >> { n92, g, n114, n200, n269, n };
assign n62 = 32'd128 >> { n42, d, c, n63, b };
assign n350 = 64'h2022202220222222 >> { n, n136, n349, m, n266, n267 };
assign n351 = 64'hbaa9babbfeedfeff >> { n232, n202, n45, h, m, i };
assign n352 = 64'h7520202020202020 >> { n275, n276, n274, n279, n280, n };
assign n353 = 64'h4045400544454005 >> { n273, n351, m, n, n352, n355 };
assign n354 = 64'h4040ea404444ee44 >> { n229, n226, n113, i, n235, m };
assign n355 = 64'h4544454455554544 >> { n200, n198, n354, n, n272, g };
assign n356 = 64'heaeaeaea40eaeaea >> { f, n153, n171, n193, n79, l };
assign n357 = 64'h0080808000888888 >> { n140, n203, n256, n257, n288, n290 };
assign n358 = 64'h000800020008000a >> { j, l, n361, n287, n356, n357 };
assign n359 = 64'h8901890188008901 >> { e, g, j, c, l, n };
assign n63 = 4'h2 >> { e, g };
assign n360 = 64'hffffdfdddfffdfdd >> { n49, f, l, n161, m, n359 };
assign n361 = 64'haaaaaaaaaaaaaa2a >> { n212, n284, n286, n285, n360, i };
assign n362 = 64'h222222222222f222 >> { n154, m, n153, k, n156, n161 };
assign n363 = 64'h0808000800080008 >> { i, j, n362, n145, n139, n147 };
assign n2 = 64'hfffffff7fff7fff7 >> { n301, k, n138, n149, n151, n363 };
assign n365 = 64'h7febd8ec20202020 >> { a, e, c, f, d, b };
assign n366 = 64'hfdfdfdfd55fdfdfd >> { j, n91, n365, n165, n105, h };
assign n367 = 64'h0f020f020f022f22 >> { m, n152, n84, n156, j, i };
assign o2 = 64'hffff7fff7fff7fff >> { k, n367, n151, n162, n302, n366 };
assign n369 = 64'h0000000080000000 >> { n, m, a, n53, n99, n136 };
assign n64 = 4'h2 >> { n65, n68 };
assign n370 = 64'h0213131313131313 >> { n92, n203, n204, n369, n201, k };
assign n371 = 32'd8 >> { n37, n197, n223, n370, n56 };
assign n372 = 64'hddd44444fff44444 >> { n232, m, g, n257, j, k };
assign n373 = 64'h0101010001010101 >> { n346, m, i, n259, n260, n258 };
assign n374 = 32'd2148042760 >> { n256, n372, m, n373, n261 };
assign n375 = 64'h0000fbf90000fff9 >> { n161, n254, n253, f, c, e };
assign n376 = 64'hf8f0f8f0f8f8f8f0 >> { n252, n375, m, n, n345, n374 };
assign l2 = 64'hffffffff7fffffff >> { n348, n338, n341, n376, n353, n358 };
assign n65 = 16'h0777 >> { n66, n44, n43, n67 };
assign n66 = 8'h08 >> { h, f, g };
assign n67 = 8'h80 >> { h, f, g };
assign n68 = 8'h08 >> { d, e, b };
assign n69 = 8'h02 >> { n297, a, n40 };
assign n34 = 32'd2416120153 >> { l, h, i, j, k };
assign n70 = 32'd521084703 >> { h, n74, n71, n72, n73 };
assign n71 = 4'h8 >> { g, e };
assign n72 = 16'h0080 >> { k, j, m, l };
assign n73 = 32'd134219784 >> { k, l, i, m, j };
assign n74 = 16'hd5f7 >> { j, i, l, m };
assign n75 = 4'h8 >> { l, m };
assign n76 = 32'd128 >> { n, g, k, h, m };
assign n77 = 32'd1423760604 >> { n82, n63, n81, n42, n80 };
assign n78 = 32'd32768 >> { j, n79, i, f, g };
assign n79 = 8'h08 >> { n, m, k };
assign n35 = 32'd538976800 >> { j, l, k, n, m };
assign n80 = 32'd128 >> { j, n, m, i, k };
assign n81 = 64'hf7f7f7f7f7f777f7 >> { e, d, g, b, c, f };
assign n82 = 8'h08 >> { c, d, a };
assign n83 = 64'hfff7fff7f7f7fff7 >> { n47, d, n60, e, c, f };
assign n84 = 4'h2 >> { h, i };
assign n85 = 8'h80 >> { c, d, b };
assign n86 = 16'haa2a >> { n88, n90, n54, n82 };
assign n87 = 32'd3749142487 >> { i, l, j, k, m };
assign n88 = 64'h0040404455555555 >> { n89, n74, n87, h, n63, n };
assign n89 = 64'hfff7ffd7ffffffdf >> { i, j, e, h, g, n75 };
assign n36 = 32'd286330897 >> { f, n49, n47, n41, n37 };
assign n90 = 32'd3149597627 >> { n92, n63, n91, n76, e };
assign n91 = 8'h08 >> { l, n33, k };
assign n92 = 4'h2 >> { i, j };
assign n93 = 32'd9076874 >> { n50, n54, e, d, n94 };
assign n94 = 8'h08 >> { b, c, a };
assign t2 = 64'hfffdfffdfffffffd >> { c, n104, n102, n103, n101, n96 };
assign n96 = 64'h50d850d850d872fa >> { n100, n98, n64, n97, n47, f };
assign n97 = 64'hdf57ffffdf57dfff >> { d, c, n47, b, n42, n46 };
assign n98 = 4'h8 >> { n99, c };
assign n99 = 4'h2 >> { d, e };
assign n37 = 16'h0080 >> { n38, n40, n33, a };
assign n100 = 8'h08 >> { c, e, d };
assign n101 = 32'd17367048 >> { b, e, n54, d, a };
assign n102 = 32'd2621472 >> { d, n61, c, b, e };
assign n103 = 64'h1232100012221020 >> { c, e, d, a, n54, b };
assign n104 = 64'h0088000800800000 >> { n44, n43, f, h, n40, g };
assign n105 = 4'h2 >> { n109, n106 };
assign n106 = 64'hd5ddf5ff55557577 >> { n108, n107, n82, e, f, g };
assign n107 = 32'd2829617160 >> { b, c, d, e, a };
assign n108 = 32'd3012899733 >> { e, d, c, a, b };
assign n109 = 32'd32768 >> { d, c, e, g, a };
assign n38 = 64'hefcdefcdefcdffdd >> { k, n39, n34, h, e, g };
assign n110 = 64'h1011111100110111 >> { n108, n107, n52, f, n112, n111 };
assign n111 = 64'h0000000000000080 >> { g, c, e, h, d, a };
assign n112 = 64'h0000000000008000 >> { g, d, c, e, h, a };
assign n113 = 4'h2 >> { k, j };
assign n114 = 4'h1 >> { l, k };
assign n115 = 64'h88888888a8888888 >> { m, k, n66, i, n116, n98 };
assign n116 = 32'd134785544 >> { n118, n117, m, n113, n67 };
assign n117 = 4'h2 >> { m, k };
assign n118 = 8'h80 >> { l, j, i };
assign n119 = 64'h5111111111111111 >> { i, g, n75, n113, n121, n120 };
assign n39 = 4'h2 >> { j, l };
assign n120 = 16'hf777 >> { a, f, b, e };
assign n121 = 64'hffffff7f7fffffff >> { l, j, g, m, h, i };
assign n122 = 64'h0000000000000080 >> { n62, n128, n129, n123, n124, n130 };
assign n123 = 64'hfdfdfdfd00fdfdfd >> { n106, i, n91, n65, e, n40 };
assign n124 = 32'd33685506 >> { n108, n78, n127, n125, n126 };
assign n125 = 32'd2860548224 >> { n53, n107, n63, n82, n80 };
assign n126 = 64'hf7fff7fff7f7f7ff >> { n120, g, n109, j, i, n79 };
assign n127 = 64'h0088000800800000 >> { n44, n43, c, h, n71, b };
assign n128 = 64'h0200020008080200 >> { f, e, c, n42, b, g };
assign n129 = 64'h020a080200080800 >> { d, f, e, n47, c, g };
endmodule

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openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif Normal file
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clock 0.503600 0.509400
G0 0.499400 0.497000
G1 0.491000 0.490800
G2 0.512600 0.511000
G10 0.332600 0.665000
G11 0.200200 0.265200
G12 0.059400 0.066000
G13 0.002600 0.003600
G14 0.130200 0.194400
G15 0.001200 0.000800
G66 0.000400 0.000800
G67 0.990600 0.009600
G117 0.997600 0.002000
G118 0.001600 0.002800
G132 0.001200 0.002400
G133 0.007000 0.009200
G22 0.250000 0.378200
G23 0.255600 0.380400
n63 0.001600 0.000006
n56 0.998200 0.000000
n57 0.002200 0.015182
n67 0.001200 0.000003
n59_1 0.000800 0.015201
n21 0.332600 0.166165
n26 0.200200 0.002222
n31 0.059400 0.205226
n36 0.002600 0.077660
n41 0.130200 0.137391
n65 0.744000 0.000000
n46 0.001200 0.000001
n51 0.000400 0.000003
n55 0.990600 0.003272
n59 0.997600 0.128971
n71 0.007000 0.216731
n75 0.250000 0.056676
n80 0.255600 0.059427

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# Benchmark "s298" written by ABC on Tue Mar 12 09:40:31 2019
.model s298
.inputs clock G0 G1 G2
.outputs G117 G132 G66 G118 G133 G67
.latch n21 G10 re clock 0
.latch n26 G11 re clock 0
.latch n31 G12 re clock 0
.latch n36 G13 re clock 0
.latch n41 G14 re clock 0
.latch n46 G15 re clock 0
.latch n51 G66 re clock 0
.latch n55 G67 re clock 0
.latch n59 G117 re clock 0
.latch n63 G118 re clock 0
.latch n67 G132 re clock 0
.latch n71 G133 re clock 0
.latch n75 G22 re clock 0
.latch n80 G23 re clock 0
.names n56 n57 G10 n63
0-0 1
11- 1
.names G15 G11 G13 G22 G14 G12 n56
01---- 1
0-0--- 1
0--0-- 1
0---1- 1
0----1 1
-11000 1
.names G14 G13 G12 G118 G11 n57
01--- 1
100-0 1
1-11- 1
-1-1- 1
.names n56 n59_1 G10 n67
0-0 1
11- 1
.names G14 G13 G12 G132 G11 n59_1
100-0 1
11-1- 1
1-11- 1
.names G0 G10 n21
00 1
.names G10 G11 G0 G12 G13 n26
010-- 1
1001- 1
100-0 1
.names G12 G0 G11 G10 n31
0011 1
100- 1
10-0 1
.names G13 G0 G11 G12 G10 n36
00111 1
1001- 1
1010- 1
10--0 1
.names n65 G14 G0 n41
000 1
110 1
.names G23 G10 G13 G11 G12 n65
1---- 0
-1100 0
.names G0 n56 n46
00 1
.names n56 G66 G14 G13 G12 n51
111-1 1
11-1- 1
1-01- 1
.names n56 G13 G14 G11 G67 G12 n55
1000-- 1
10-1-0 1
111-1- 1
1-1-11 1
.names n56 G13 G117 G14 G12 G11 n59
10-0-- 1
10--01 1
1111-- 1
1-111- 1
.names n56 G14 G12 G13 G133 G11 n71
1010-1 1
111-1- 1
11-11- 1
.names G2 G22 G0 n75
010 1
100 1
.names G1 G23 G0 n80
010 1
100 1
.end

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/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
module s298(clock, G0, G1, G2, G117, G132, G66, G118, G133, G67);
input G0;
input G1;
(* init = 1'h0 *)
reg G10 = 1'h0;
(* init = 1'h0 *)
reg G11 = 1'h0;
(* init = 1'h0 *)
output G117;
reg G117 = 1'h0;
(* init = 1'h0 *)
output G118;
reg G118 = 1'h0;
(* init = 1'h0 *)
reg G12 = 1'h0;
(* init = 1'h0 *)
reg G13 = 1'h0;
(* init = 1'h0 *)
output G132;
reg G132 = 1'h0;
(* init = 1'h0 *)
output G133;
reg G133 = 1'h0;
(* init = 1'h0 *)
reg G14 = 1'h0;
(* init = 1'h0 *)
reg G15 = 1'h0;
input G2;
(* init = 1'h0 *)
reg G22 = 1'h0;
(* init = 1'h0 *)
reg G23 = 1'h0;
(* init = 1'h0 *)
output G66;
reg G66 = 1'h0;
(* init = 1'h0 *)
output G67;
reg G67 = 1'h0;
input clock;
wire n21;
wire n26;
wire n31;
wire n36;
wire n41;
wire n46;
wire n51;
wire n55;
wire n56;
wire n57;
wire n59;
wire n59_1;
wire n63;
wire n65;
wire n67;
wire n71;
wire n75;
wire n80;
always @(posedge clock)
G10 <= n21;
always @(posedge clock)
G118 <= n63;
always @(posedge clock)
G132 <= n67;
always @(posedge clock)
G133 <= n71;
always @(posedge clock)
G22 <= n75;
always @(posedge clock)
G23 <= n80;
always @(posedge clock)
G11 <= n26;
always @(posedge clock)
G12 <= n31;
always @(posedge clock)
G13 <= n36;
always @(posedge clock)
G14 <= n41;
always @(posedge clock)
G15 <= n46;
always @(posedge clock)
G66 <= n51;
always @(posedge clock)
G67 <= n55;
always @(posedge clock)
G117 <= n59;
assign n63 = 8'h8d >> { G10, n57, n56 };
assign n56 = 64'h55555555555545d5 >> { G12, G14, G22, G13, G11, G15 };
assign n57 = 32'd3963940422 >> { G11, G118, G12, G13, G14 };
assign n67 = 8'h8d >> { G10, n59_1, n56 };
assign n59_1 = 32'd2818615810 >> { G11, G132, G12, G13, G14 };
assign n21 = 4'h1 >> { G10, G0 };
assign n26 = 32'd100926982 >> { G13, G12, G0, G11, G10 };
assign n31 = 16'h1222 >> { G10, G11, G0, G12 };
assign n36 = 32'd304095778 >> { G10, G12, G11, G0, G13 };
assign n41 = 8'h09 >> { G0, G14, n65 };
assign n65 = 32'd1431655701 >> { G12, G11, G13, G10, G23 };
assign n46 = 4'h1 >> { n56, G0 };
assign n51 = 32'd2323679744 >> { G12, G13, G14, G66, n56 };
assign n55 = 64'ha0a20002a2822202 >> { G12, G67, G11, G14, G13, n56 };
assign n59 = 64'ha022a222a0228022 >> { G11, G12, G14, G117, G13, n56 };
assign n71 = 64'h88a0002088800000 >> { G11, G133, G13, G12, G14, n56 };
assign n75 = 8'h06 >> { G0, G22, G2 };
assign n80 = 8'h06 >> { G0, G23, G1 };
endmodule

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@ -0,0 +1,644 @@
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i_9_ 0.507000 0.499400
i_10_ 0.485600 0.503800
i_11_ 0.505200 0.499400
i_12_ 0.496800 0.500000
i_13_ 0.498600 0.506800
i_14_ 0.505000 0.504200
i_15_ 0.494600 0.491200
i_16_ 0.495800 0.501200
i_17_ 0.499600 0.495000
i_18_ 0.507000 0.507000
i_19_ 0.501400 0.504200
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i_23_ 0.504600 0.497200
i_24_ 0.509000 0.508400
i_25_ 0.506600 0.497800
i_26_ 0.501800 0.491800
i_27_ 0.501200 0.492600
i_28_ 0.491000 0.518800
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i_31_ 0.498200 0.494400
i_32_ 0.503600 0.496200
i_33_ 0.498600 0.483600
i_34_ 0.506800 0.495000
i_35_ 0.498800 0.503000
i_36_ 0.489800 0.503200
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n595 0.856600 0.032896
n596 0.790200 0.130894
n597 0.246400 0.006546
n598 0.998000 0.000008
n599 0.997000 0.000006
n600 0.999600 0.000008
o_3_ 0.272600 0.289725
n602 0.946800 0.005524
n603 0.122400 0.276226
n604 0.011200 0.000128
n605 0.387000 0.096857
n606 0.260400 0.088321
n607 0.024400 0.000595
n608 0.997200 0.174526
o_4_ 0.020000 0.046547
n610 0.011400 0.059408
n611 0.999800 0.001070
n612 0.497800 0.000586
n613 0.024200 0.024699
n614 0.000000 0.090009
n615 0.998600 0.228596
n616 0.997600 0.061960
o_6_ 0.013400 0.028797
n618 0.000600 0.000014
n619 0.044200 0.089238
n620 0.998800 0.000799
n621 0.999600 0.000906
o_7_ 0.254400 0.001072
n623 0.992600 0.064172
n624 0.992400 0.006308
n625 0.015000 0.000489
n626 0.996200 0.121653
o_16_ 0.006600 0.000004
n628 0.985600 0.094527
n629 0.980200 0.000000
n630 0.964200 0.000732
n631 0.989400 0.000003
o_20_ 0.019000 0.062154
n633 0.109200 0.015870
n634 0.001600 0.000003
n635 0.333600 0.016807
n636 0.003200 0.174359
n637 0.868600 0.079789
n638 0.015200 0.019607
o_21_ 0.572400 0.109770
n640 0.728600 0.048073
n641 0.971600 0.010642
n642 1.000000 0.000549
n643 0.999600 0.000000
o_25_ 0.002800 0.000002
n645 0.979600 0.000626
o_34_ 0.268600 0.000353
n647 0.282800 0.007470
n648 0.995000 0.000000
n649 0.194800 0.019563
n650 0.982400 0.078743
n651 0.997000 0.018185
n652 0.992600 0.000018
o_5_ 0.022200 0.049066
n654 0.003200 0.278647
n655 0.496400 0.106553
n656 0.006800 0.155990
n657 0.004400 0.000947
n658 0.997000 0.002592
n659 0.803000 0.021488
n660 0.999000 0.000001
o_17_ 0.255800 0.000004
n662 0.064800 0.119146
o_22_ 0.029600 0.095576
n664 0.999800 0.028124
o_30_ 0.000400 0.000799
n666 0.934400 0.096075
o_23_ 0.310800 0.010204
n668 0.991600 0.000106
n669 0.993000 0.000009
n670 0.988000 0.000000
n671 0.008200 0.000078
n672 0.994000 0.012849
n673 0.758000 0.098172
n674 0.999400 0.004734
n675 0.995400 0.000000
n676 0.186000 0.076163
n677 0.069600 0.086139
n678 0.978400 0.000000
n679 0.692200 0.032154
n680 0.966000 0.000115
n681 0.719200 0.000801

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16
openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act Normal file
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@ -0,0 +1,16 @@
clk 0.5 0.2
a 0.5 0.2
b 0.5 0.2
c 0.5 0.2
XOR 0.5 0.2
XNOR 0.5 0.2
OR 0.5 0.2
NOR 0.5 0.2
AND 0.5 0.2
NAND 0.5 0.2
XOR_sync 0.5 0.2
XNOR_sync 0.5 0.2
OR_sync 0.5 0.2
NOR_sync 0.5 0.2
AND_sync 0.5 0.2
NAND_sync 0.5 0.2

40
openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif Normal file
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@ -0,0 +1,40 @@
.model K4n4_test
.inputs clk a b c
.outputs XOR XNOR AND NAND OR NOR XOR_sync XNOR_sync AND_sync NAND_sync OR_sync NOR_sync
.names a b c XOR
100 1
010 1
001 1
111 1
.names a b c XNOR
011 1
101 1
110 1
000 1
.names a b c AND
111 1
.names a b c NAND
0-- 1
-0- 1
--0 1
.names a b c OR
1-- 1
-1- 1
--1 1
.names a b c NOR
000 1
.latch XOR XOR_sync re clk 0
.latch XNOR XNOR_sync re clk 0
.latch OR OR_sync re clk 0
.latch NOR NOR_sync re clk 0
.latch AND AND_sync re clk 0
.latch NAND NAND_sync re clk 0
.end

54
openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v Normal file
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@ -0,0 +1,54 @@
`timescale 1ns / 1ps
module K4n4_test (
clk,
a,
b,
c,
XOR,
XNOR,
AND,
NAND,
OR,
NOR,
XOR_sync,
XNOR_sync,
AND_sync,
NAND_sync,
OR_sync,
NOR_sync );
input wire clk;
input wire a;
input wire b;
input wire c;
output wire XOR;
output wire XNOR;
output wire AND;
output wire NAND;
output wire OR;
output wire NOR;
output reg XOR_sync;
output reg XNOR_sync;
output reg AND_sync;
output reg NAND_sync;
output reg OR_sync;
output reg NOR_sync;
assign XOR = a ^ b ^ c;
assign XNOR = !XOR;
assign OR = a || b || c;
assign NOR = !( a || b || c);
assign AND = a && b && c;
assign NAND = !(a && b && c);
always @(posedge clk) begin
XOR_sync = XOR;
XNOR_sync = XNOR;
OR_sync = OR;
NOR_sync = NOR;
AND_sync = AND;
NAND_sync = NAND;
end
endmodule

0
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0
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8
openfpga_flow/tasks/blif_vpr_flow/config/task.conf
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@ -25,12 +25,12 @@ arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO
#arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
[SYNTHESIS_PARAM]
bench0_top = test_modes
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
bench0_chan_width = 300
#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
@ -60,5 +60,7 @@ vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_verilog_explicit_mapping=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=

43
openfpga_flow/tasks/explicit_verilog/config/task.conf Normal file
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@ -0,0 +1,43 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
#arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
[SYNTHESIS_PARAM]
bench0_top = test_modes
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT]
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_x2p_compact_routing_hierarchy=
vpr_fpga_verilog_explicit_mapping=
end_flow_with_test=

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openfpga_flow/tasks/mcnc_big20/config/task.conf Normal file
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@ -0,0 +1,156 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
#arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
[BENCHMARKS]
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
[SYNTHESIS_PARAM]
# Benchmark alu4
bench0_top = alu4
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.v
# Benchmark apex2
bench1_top = apex2
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.v
# Benchmark apex4
bench2_top = apex4
bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.act
bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.v
# Benchmark bigkey
bench3_top = bigkey
bench3_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.act
bench3_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.v
# Benchmark clma
bench4_top = clma
bench4_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.act
bench4_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.v
# Benchmark des
bench5_top = des
bench5_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.act
bench5_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.v
# Benchmark diffeq
bench6_top = diffeq
bench6_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.act
bench6_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.v
# Benchmark dsip
bench7_top = dsip
bench7_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.act
bench7_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.v
# Benchmark elliptic
bench8_top = elliptic
bench8_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.act
bench8_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.v
# Benchmark ex1010
bench9_top = ex1010
bench9_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.act
bench9_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.v
# Benchmark ex5p
bench10_top = ex5p
bench10_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.act
bench10_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.v
# Benchmark frisc
bench11_top = frisc
bench11_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.act
bench11_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.v
# Benchmark misex3
bench12_top = misex3
bench12_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.act
bench12_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.v
# Benchmark pdc
bench13_top = pdc
bench13_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.act
bench13_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.v
# Benchmark s298
bench14_top = s298
bench14_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act
bench14_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v
# Benchmark s38417
bench15_top = s38417
bench15_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.act
bench15_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.v
# Benchmark s38584
bench16_top = s38584
bench16_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.act
bench16_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.v
# Benchmark seq
bench17_top = seq
bench17_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.act
bench17_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.v
# Benchmark spla
bench18_top = spla
bench18_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.act
bench18_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.v
# Benchmark tseng
bench19_top = tseng
bench19_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.act
bench19_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.v
#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
#fix_route_chan_width=300
#vpr_fpga_verilog_include_icarus_simulator=
#vpr_fpga_verilog_formal_verification_top_netlist=
#vpr_fpga_verilog_include_timing=
#vpr_fpga_verilog_include_signal_init=
#vpr_fpga_verilog_print_autocheck_top_testbench=
#vpr_fpga_bitstream_generator=
#vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
##vpr_fpga_x2p_compact_routing_hierarchy=
#end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_verilog_explicit_mapping=
vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=

58
openfpga_flow/tasks/multi_mode/config/task.conf Normal file
View File

@ -0,0 +1,58 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
[SYNTHESIS_PARAM]
bench0_top = K4n4_test
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
bench0_chan_width = 100
#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
#fix_route_chan_width=300
#vpr_fpga_verilog_include_icarus_simulator=
#vpr_fpga_verilog_formal_verification_top_netlist=
#vpr_fpga_verilog_include_timing=
#vpr_fpga_verilog_include_signal_init=
#vpr_fpga_verilog_print_autocheck_top_testbench=
#vpr_fpga_bitstream_generator=
#vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
#end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0]
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_verilog_explicit_mapping=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=

58
openfpga_flow/tasks/s298/config/task.conf Normal file
View File

@ -0,0 +1,58 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N6_sram_chain_FC_behavioral_verilog_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
[SYNTHESIS_PARAM]
bench0_top = s298
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.v
bench0_chan_width = 100
#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
#fix_route_chan_width=300
#vpr_fpga_verilog_include_icarus_simulator=
#vpr_fpga_verilog_formal_verification_top_netlist=
#vpr_fpga_verilog_include_timing=
#vpr_fpga_verilog_include_signal_init=
#vpr_fpga_verilog_print_autocheck_top_testbench=
#vpr_fpga_bitstream_generator=
#vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
#end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0]
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_verilog_explicit_mapping=
vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=

58
openfpga_flow/tasks/single_mode/config/task.conf Normal file
View File

@ -0,0 +1,58 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
[SYNTHESIS_PARAM]
bench0_top = K4n4_test
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
bench0_chan_width = 100
#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
#fix_route_chan_width=300
#vpr_fpga_verilog_include_icarus_simulator=
#vpr_fpga_verilog_formal_verification_top_netlist=
#vpr_fpga_verilog_include_timing=
#vpr_fpga_verilog_include_signal_init=
#vpr_fpga_verilog_print_autocheck_top_testbench=
#vpr_fpga_bitstream_generator=
#vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
#vpr_fpga_verilog_print_sdc_pnr=
#vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
#end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0]
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_verilog_explicit_mapping=
vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=

6
openfpga_flow/tasks/tileable_routing/config/task.conf
View File

@ -18,12 +18,12 @@ fpga_flow=vpr_blif
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
[SYNTHESIS_PARAM]
bench0_top = test_modes
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
bench0_chan_width = 300
[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]

9
tutorials/building.md
View File

@ -1,7 +1,6 @@
# How to build?
## Dependencies
OpenFPGA requires all the following dependencies:
- autoconf
- automake
@ -39,10 +38,9 @@ OpenFPGA requires all the following dependencies:
- qt5-default
## Docker
If all these dependancies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). To ease customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command:
If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command:
- docker run lnis/open_fpga:release <br />
*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".*
*Warning: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as "-v".*
Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands:
- docker build . -t open_fpga
@ -50,8 +48,7 @@ Otherwise, a container where you can build OpenFPGA yourself can be created with
[*docker download link*](https://www.docker.com/products/docker-desktop)
## Building
To build the tool you have to go in OpenFPGA folder and do:
To build the tool, go in the OpenFPGA folder and do:
- mkdir build && cd build
- cmake .. -DCMAKE_BUILD_TYPE=debug
- make (*WARNING using docker you cannot use "make -j", errors will happen*)

77
vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
View File

@ -49,7 +49,6 @@
#include "check_circuit_library.h"
/************************************************************************
* Circuit models have unique names, return the number of errors
* If not found, we give an error
@ -394,6 +393,82 @@ size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
num_err++;
}
/* Check all the global ports which sare the same name also share the same attributes:
* default_value, is_config, is_reset, is_set etc.
*/
std::vector<CircuitPortId> global_ports;
/* Collect all the global ports */
for (auto port : circuit_lib.ports()) {
/* By pass non-global ports*/
if (false == circuit_lib.port_is_global(port)) {
continue;
}
global_ports.push_back(port);
}
for (size_t iport = 0; iport < global_ports.size() - 1; ++iport) {
for (size_t jport = iport + 1; jport < global_ports.size(); ++jport) {
/* Bypass those do not share the same name */
if (0 != circuit_lib.port_lib_name(global_ports[iport]).compare(circuit_lib.port_lib_name(global_ports[jport]))) {
continue;
}
/* Check if a same port share the same attributes */
CircuitModelId iport_parent_model = circuit_lib.port_parent_model(global_ports[iport]);
CircuitModelId jport_parent_model = circuit_lib.port_parent_model(global_ports[jport]);
if (circuit_lib.port_default_value(global_ports[iport]) != circuit_lib.port_default_value(global_ports[jport])) {
vpr_printf(TIO_MESSAGE_ERROR,
"Global ports %s from circuit model %s and %s share the same name but have different dfefault values(%lu and %lu)!\n",
circuit_lib.port_lib_name(global_ports[iport]).c_str(),
circuit_lib.model_name(iport_parent_model).c_str(),
circuit_lib.model_name(jport_parent_model).c_str(),
circuit_lib.port_default_value(global_ports[iport]),
circuit_lib.port_default_value(global_ports[jport])
);
num_err++;
}
if (circuit_lib.port_is_reset(global_ports[iport]) != circuit_lib.port_is_reset(global_ports[jport])) {
vpr_printf(TIO_MESSAGE_ERROR,
"Global ports %s from circuit model %s and %s share the same name but have different is_reset attributes!\n",
circuit_lib.port_lib_name(global_ports[iport]).c_str(),
circuit_lib.model_name(iport_parent_model).c_str(),
circuit_lib.model_name(jport_parent_model).c_str()
);
num_err++;
}
if (circuit_lib.port_is_set(global_ports[iport]) != circuit_lib.port_is_set(global_ports[jport])) {
vpr_printf(TIO_MESSAGE_ERROR,
"Global ports %s from circuit model %s and %s share the same name but have different is_set attributes!\n",
circuit_lib.port_lib_name(global_ports[iport]).c_str(),
circuit_lib.model_name(iport_parent_model).c_str(),
circuit_lib.model_name(jport_parent_model).c_str()
);
num_err++;
}
if (circuit_lib.port_is_config_enable(global_ports[iport]) != circuit_lib.port_is_config_enable(global_ports[jport])) {
vpr_printf(TIO_MESSAGE_ERROR,
"Global ports %s from circuit model %s and %s share the same name but have different is_config_enable attributes!\n",
circuit_lib.port_lib_name(global_ports[iport]).c_str(),
circuit_lib.model_name(iport_parent_model).c_str(),
circuit_lib.model_name(jport_parent_model).c_str()
);
num_err++;
}
if (circuit_lib.port_is_prog(global_ports[iport]) != circuit_lib.port_is_prog(global_ports[jport])) {
vpr_printf(TIO_MESSAGE_ERROR,
"Global ports %s from circuit model %s and %s share the same name but have different is_prog attributes!\n",
circuit_lib.port_lib_name(global_ports[iport]).c_str(),
circuit_lib.model_name(iport_parent_model).c_str(),
circuit_lib.model_name(jport_parent_model).c_str()
);
num_err++;
}
}
}
return num_err;
}

149
vpr7_x2p/libarchfpga/SRC/circuit_library_utils.cpp
View File

@ -91,3 +91,152 @@ std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary&
return regular_sram_ports;
}
/********************************************************************
* Find mode select sram ports of a circuit model
*******************************************************************/
std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true);
std::vector<CircuitPortId> mode_select_sram_ports;
for (const auto& port : sram_ports) {
if (false == circuit_lib.port_is_mode_select(port)) {
continue;
}
mode_select_sram_ports.push_back(port);
}
return mode_select_sram_ports;
}
/********************************************************************
* Find the number of shared configuration bits for a ReRAM circuit
* TODO: this function is subjected to be changed due to ReRAM-based SRAM cell design!!!
*******************************************************************/
static
size_t find_rram_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& rram_model,
const e_sram_orgz& sram_orgz_type) {
size_t num_shared_config_bits = 0;
/* Branch on the organization of configuration protocol */
switch (sram_orgz_type) {
case SPICE_SRAM_STANDALONE:
case SPICE_SRAM_SCAN_CHAIN:
break;
case SPICE_SRAM_MEMORY_BANK: {
/* Find BL/WL ports */
std::vector<CircuitPortId> blb_ports = circuit_lib.model_ports_by_type(rram_model, SPICE_MODEL_PORT_BLB);
for (auto blb_port : blb_ports) {
num_shared_config_bits = std::max((int)num_shared_config_bits, (int)circuit_lib.port_size(blb_port) - 1);
}
break;
}
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,[LINE%d]) Invalid type of SRAM organization!\n",
__FILE__, __LINE__);
exit(1);
}
return num_shared_config_bits;
}
/********************************************************************
* A generic function to find the number of shared configuration bits
* for circuit model
* It will return 0 for CMOS circuits
* It will return the maximum shared configuration bits across ReRAM models
*
* Note: This function may give WRONG results when all the SRAM ports
* are not properly linked to its circuit models!
* So, it should be called after the SRAM linking is done!!!
*
* IMPORTANT: This function should NOT be used to find the number of shared configuration bits
* for a multiplexer, because the multiplexer size is determined during
* the FPGA architecture generation (NOT during the XML parsing).
*******************************************************************/
size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model,
const e_sram_orgz& sram_orgz_type) {
size_t num_shared_config_bits = 0;
std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
for (auto sram_port : sram_ports) {
CircuitModelId sram_model = circuit_lib.port_tri_state_model(sram_port);
VTR_ASSERT( true == circuit_lib.valid_model_id(sram_model) );
/* Depend on the design technolgy of SRAM model, the number of configuration bits will be different */
switch (circuit_lib.design_tech_type(sram_model)) {
case SPICE_MODEL_DESIGN_CMOS:
/* CMOS circuit do not need shared configuration bits */
break;
case SPICE_MODEL_DESIGN_RRAM:
/* RRAM circuit do need shared configuration bits, but it is subjected to the largest one among different SRAM models */
num_shared_config_bits = std::max((int)num_shared_config_bits, (int)find_rram_circuit_num_shared_config_bits(circuit_lib, sram_model, sram_orgz_type));
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,[LINE%d]) Invalid design technology for SRAM model!\n",
__FILE__, __LINE__);
exit(1);
}
}
return num_shared_config_bits;
}
/********************************************************************
* A generic function to find the number of configuration bits
* for circuit model
* It will sum up the sizes of all the sram ports
*
* IMPORTANT: This function should NOT be used to find the number of configuration bits
* for a multiplexer, because the multiplexer size is determined during
* the FPGA architecture generation (NOT during the XML parsing).
*******************************************************************/
size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
size_t num_config_bits = 0;
std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM);
for (auto sram_port : sram_ports) {
num_config_bits += circuit_lib.port_size(sram_port);
}
return num_config_bits;
}
/********************************************************************
* A generic function to find all the global ports in a circuit library
*
* IMPORTANT: This function will uniquify the global ports whose share
* share the same name !!!
*******************************************************************/
std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib) {
std::vector<CircuitPortId> global_ports;
for (auto port : circuit_lib.ports()) {
/* By pass non-global ports*/
if (false == circuit_lib.port_is_global(port)) {
continue;
}
/* Check if a same port with the same name has already been in the list */
bool add_to_list = true;
for (const auto& global_port : global_ports) {
if (0 == circuit_lib.port_lib_name(port).compare(circuit_lib.port_lib_name(global_port))) {
/* Same name, skip list update */
add_to_list = false;
break;
}
}
if (true == add_to_list) {
/* Add the global_port to the list */
global_ports.push_back(port);
}
}
return global_ports;
}

13
vpr7_x2p/libarchfpga/SRC/circuit_library_utils.h
View File

@ -8,6 +8,7 @@
/* Standard header files required go first */
#include <vector>
#include "spice_types.h"
#include "circuit_library.h"
std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circuit_lib,
@ -16,4 +17,16 @@ std::vector<CircuitModelId> find_circuit_sram_models(const CircuitLibrary& circu
std::vector<CircuitPortId> find_circuit_regular_sram_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
std::vector<CircuitPortId> find_circuit_mode_select_sram_ports(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
size_t find_circuit_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model,
const e_sram_orgz& sram_orgz_type);
size_t find_circuit_num_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrary& circuit_lib);
#endif

74
vpr7_x2p/libarchfpga/SRC/device_port.cpp
View File

@ -1,6 +1,8 @@
#include <numeric>
#include <algorithm>
#include <limits>
#include <cassert>
#include "vtr_assert.h"
#include "device_port.h"
@ -63,6 +65,52 @@ std::string BasicPort::get_name() const {
return name_;
}
/* Make a range of the pin indices */
std::vector<size_t> BasicPort::pins() const {
std::vector<size_t> pin_indices;
/* Return if the port is invalid */
if (false == is_valid()) {
return pin_indices; /* Return an empty vector */
}
/* For valid ports, create a vector whose length is the port width */
pin_indices.resize(get_width());
/* Fill in an incremental sequence */
std::iota(pin_indices.begin(), pin_indices.end(), get_lsb());
/* Ensure the last one is MSB */
VTR_ASSERT(get_msb() == pin_indices.back());
return pin_indices;
}
/* Check if a port can be merged with this port: their name should be the same */
bool BasicPort::mergeable(const BasicPort& portA) const {
return (0 == this->get_name().compare(portA.get_name()));
}
/* Check if a port is contained by this port:
* this function will check if the (LSB, MSB) of portA
* is contained by the (LSB, MSB) of this port
*/
bool BasicPort::contained(const BasicPort& portA) const {
return ( lsb_ <= portA.get_lsb() && portA.get_msb() <= msb_ );
}
/* Overloaded operators */
/* Two ports are the same only when:
* 1. port names are the same
* 2. LSBs are the same
* 3. MSBs are the same
*/
bool BasicPort::operator== (const BasicPort& portA) const {
if ( (0 == this->get_name().compare(portA.get_name()))
&& (this->get_lsb() == portA.get_lsb())
&& (this->get_msb() == portA.get_msb()) ) {
return true;
}
return false;
}
/* Mutators */
/* copy */
void BasicPort::set(const BasicPort& basic_port) {
@ -188,7 +236,7 @@ void BasicPort::reset() {
void BasicPort::combine(const BasicPort& port) {
/* LSB follows the current LSB */
/* MSB increases */
assert( 0 < port.get_width() ); /* Make sure port is valid */
VTR_ASSERT(0 < port.get_width() ); /* Make sure port is valid */
/* If current port is invalid, we do not combine */
if (0 == get_width()) {
return;
@ -198,6 +246,28 @@ void BasicPort::combine(const BasicPort& port) {
return;
}
/* A restricted combine function for two ports,
* Following conditions will be applied:
* 1. the two ports have the same name
* Note: you must run mergable() function first
* to make sure this assumption is valid
* 2. the new MSB will be the maximum MSB of the two ports
* 3. the new LSB will be the minimum LSB of the two ports
* 4. both ports should be valid!!!
*/
void BasicPort::merge(const BasicPort& portA) {
VTR_ASSERT(true == this->mergeable(portA));
VTR_ASSERT(true == this->is_valid() && true == portA.is_valid());
/* We skip merging if the portA is already contained by this port */
if (true == this->contained(portA)) {
return;
}
/* LSB follows the minium LSB of the two ports */
lsb_ = std::min((int)lsb_, (int)portA.get_lsb());
/* MSB follows the minium MSB of the two ports */
msb_ = std::max((int)msb_, (int)portA.get_msb());
return;
}
/* Internal functions */
/* Make a port to be invalid: msb < lsb */

7
vpr7_x2p/libarchfpga/SRC/device_port.h
View File

@ -6,6 +6,7 @@
#define DEVICE_PORT_H
#include <string>
#include <vector>
/* A basic port */
class BasicPort {
@ -16,12 +17,17 @@ class BasicPort {
BasicPort(const std::string& name, const size_t& lsb, const size_t& msb);
BasicPort(const std::string& name, const size_t& width);
BasicPort(const BasicPort& basic_port); /* Copy constructor */
public: /* Overloaded operators */
bool operator== (const BasicPort& portA) const;
public: /* Accessors */
size_t get_width() const; /* get the port width */
size_t get_msb() const; /* get the LSB */
size_t get_lsb() const; /* get the LSB */
std::string get_name() const; /* get the name */
bool is_valid() const; /* check if port size is valid > 0 */
std::vector<size_t> pins() const; /* Make a range of the pin indices */
bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */
bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */
public: /* Mutators */
void set(const BasicPort& basic_port); /* copy */
void set_name(const std::string& name); /* set the port LSB and MSB */
@ -35,6 +41,7 @@ class BasicPort {
bool counter_rotate(const size_t& offset); /* counter rotate */
void reset(); /* Reset to initial port */
void combine(const BasicPort& port); /* Combine two ports */
void merge(const BasicPort& portA);
private: /* internal functions */
void make_invalid(); /* Make a port invalid */
private: /* Internal Data */

2
vpr7_x2p/libarchfpga/SRC/linkedlist.h
View File

@ -1,6 +1,8 @@
#ifndef LINKEDLIST_H
#define LINKEDLIST_H
#include "util.h"
/*General Purpose Linked List*/
typedef struct s_llist t_llist;
struct s_llist

1
vpr7_x2p/vpr/SRC/base/vpr_types.h
View File

@ -245,6 +245,7 @@ typedef struct s_logical_block {
/* Xifan TANG: SPICE model support*/
/* For mapping */
CircuitModelId mapped_circuit_model;
t_spice_model* mapped_spice_model;
int mapped_spice_model_index; /* index of spice_model in completed FPGA netlist */
int temp_used;

252
vpr7_x2p/vpr/SRC/device/mux_graph.cpp
View File

@ -3,6 +3,7 @@
* data structures in mux_graph.h
*************************************************/
#include <cmath>
#include <list>
#include <map>
#include <algorithm>
@ -45,15 +46,24 @@ MuxGraph::node_range MuxGraph::nodes() const {
/* Find the non-input nodes */
std::vector<MuxNodeId> MuxGraph::non_input_nodes() const {
/* Must be an valid graph */
VTR_ASSERT_SAFE(valid_mux_graph());
std::vector<MuxNodeId> node_list;
for (const auto& node : nodes()) {
/* Bypass any nodes which are not OUTPUT and INTERNAL */
if (MUX_INPUT_NODE == node_types_[node]) {
continue;
/* Build the node list, level by level */
for (size_t level = 0; level < num_node_levels(); ++level) {
for (size_t node_type = 0; node_type < size_t(NUM_MUX_NODE_TYPES); ++node_type) {
/* Bypass any nodes which are not OUTPUT and INTERNAL */
if (size_t(MUX_INPUT_NODE) == node_type) {
continue;
}
/* Reach here, this is either an OUTPUT or INTERNAL node */
for (auto node : node_lookup_[level][node_type]) {
node_list.push_back(node);
}
}
/* Reach here, this is either an OUTPUT or INTERNAL node */
node_list.push_back(node);
}
return node_list;
}
@ -73,6 +83,14 @@ std::vector<size_t> MuxGraph::levels() const {
return graph_levels;
}
std::vector<size_t> MuxGraph::node_levels() const {
std::vector<size_t> graph_levels;
for (size_t lvl = 0; lvl < num_node_levels(); ++lvl) {
graph_levels.push_back(lvl);
}
return graph_levels;
}
/**************************************************
* Public Accessors: Data query
*************************************************/
@ -174,6 +192,14 @@ size_t MuxGraph::num_memory_bits_at_level(const size_t& level) const {
return mem_lookup_[level].size();
}
/* Return memory id at level */
std::vector<MuxMemId> MuxGraph::memories_at_level(const size_t& level) const {
/* need to check if the graph is valid or not */
VTR_ASSERT_SAFE(valid_level(level));
VTR_ASSERT_SAFE(valid_mux_graph());
return mem_lookup_[level];
}
/* Find the number of nodes at a given level in the MUX graph */
size_t MuxGraph::num_nodes_at_level(const size_t& level) const {
/* validate the level numbers */
@ -261,6 +287,43 @@ std::vector<size_t> MuxGraph::branch_sizes() const {
return branch;
}
/* Find the sizes of each branch of a MUX at a given level */
std::vector<size_t> MuxGraph::branch_sizes(const size_t& level) const {
std::vector<size_t> branch;
/* Visit each internal nodes/output nodes and find the the number of incoming edges */
for (auto node : node_ids_ ) {
/* Bypass input nodes */
if ( (MUX_OUTPUT_NODE != node_types_[node])
&& (MUX_INTERNAL_NODE != node_types_[node]) ) {
continue;
}
/* Bypass nodes that is not at the level */
if ( level != node_levels_[node]) {
continue;
}
size_t branch_size = node_in_edges_[node].size();
/* make sure the branch size is valid */
VTR_ASSERT_SAFE(valid_mux_implementation_num_inputs(branch_size));
/* Nodes with the same number of incoming edges, indicate the same size of branch circuit */
std::vector<size_t>::iterator it;
it = std::find(branch.begin(), branch.end(), branch_size);
/* if already exists a branch with the same size, skip updating the vector */
if (it != branch.end()) {
continue;
}
branch.push_back(branch_size);
}
/* Sort the branch by size */
std::sort(branch.begin(), branch.end());
return branch;
}
/* Build a subgraph from the given node
* The strategy is very simple, we just
* extract a 1-level graph from here
@ -391,15 +454,29 @@ MuxInputId MuxGraph::input_id(const MuxNodeId& node_id) const {
return node_input_ids_[node_id];
}
/* Get the input id of a given node */
/* Identify if the node is an input of the MUX */
bool MuxGraph::is_node_input(const MuxNodeId& node_id) const {
/* Validate node id */
VTR_ASSERT(true == valid_node_id(node_id));
return (MUX_INPUT_NODE == node_types_[node_id]);
}
/* Get the output id of a given node */
MuxOutputId MuxGraph::output_id(const MuxNodeId& node_id) const {
/* Validate node id */
VTR_ASSERT(valid_node_id(node_id));
/* Must be an input */
/* Must be an output */
VTR_ASSERT(MUX_OUTPUT_NODE == node_types_[node_id]);
return node_output_ids_[node_id];
}
/* Identify if the node is an output of the MUX */
bool MuxGraph::is_node_output(const MuxNodeId& node_id) const {
/* Validate node id */
VTR_ASSERT(true == valid_node_id(node_id));
return (MUX_OUTPUT_NODE == node_types_[node_id]);
}
/* Get the node id of a given input */
MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const {
/* Use the node_lookup to accelerate the search */
@ -414,6 +491,21 @@ MuxNodeId MuxGraph::node_id(const MuxInputId& input_id) const {
return MuxNodeId::INVALID();
}
/* Get the node id of a given output */
MuxNodeId MuxGraph::node_id(const MuxOutputId& output_id) const {
/* Use the node_lookup to accelerate the search */
for (const auto& lvl : node_lookup_) {
for (const auto& cand_node : lvl[MUX_OUTPUT_NODE]) {
if (output_id == node_output_ids_[cand_node]) {
return cand_node;
}
}
}
return MuxNodeId::INVALID();
}
/* Get the node id w.r.t. the node level and node_index at the level
* Return an invalid value if not found
*/
@ -448,19 +540,41 @@ MuxNodeId MuxGraph::node_id(const size_t& node_level, const size_t& node_index_a
return ret_node;
}
/* Decode memory bits based on an input id */
std::vector<size_t> MuxGraph::decode_memory_bits(const MuxInputId& input_id) const {
/* Decode memory bits based on an input id and an output id */
vtr::vector<MuxMemId, bool> MuxGraph::decode_memory_bits(const MuxInputId& input_id,
const MuxOutputId& output_id) const {
/* initialize the memory bits: TODO: support default value */
std::vector<size_t> mem_bits(mem_ids_.size(), 0);
vtr::vector<MuxMemId, bool> mem_bits(mem_ids_.size(), false);
/* valid the input */
/* valid the input and output */
VTR_ASSERT_SAFE(valid_input_id(input_id));
VTR_ASSERT_SAFE(valid_output_id(output_id));
/* Route the input to the output and update mem */
MuxNodeId next_node = node_id(input_id);
while ( 0 < node_out_edges_[next_node].size() ) {
VTR_ASSERT_SAFE (1 == node_out_edges_[next_node].size());
MuxEdgeId edge = node_out_edges_[next_node][0];
/* Mark all the nodes as not visited */
vtr::vector<MuxNodeId, bool> visited(nodes().size(), false);
/* Create a queue for Breadth-First Search */
std::list<MuxNodeId> queue;
/* Mark the input node as visited and enqueue it */
visited[node_id(input_id)] = true;
queue.push_back(node_id(input_id));
/* Create a flag to indicate if the route is success or not */
bool route_success = false;
while(!queue.empty()) {
/* Dequeue a mux node from queue,
* we will walk through all the fan-in of this node in this loop
*/
MuxNodeId node_to_expand = queue.front();
queue.pop_front();
/* Get all fan-in nodes of the dequeued node
* If the node has not been visited,
* then mark it visited and enqueue it
*/
VTR_ASSERT_SAFE (1 == node_out_edges_[node_to_expand].size());
MuxEdgeId edge = node_out_edges_[node_to_expand][0];
/* Configure the mem bits:
* if inv_mem is enabled, it means 0 to enable this edge
@ -469,25 +583,113 @@ std::vector<size_t> MuxGraph::decode_memory_bits(const MuxInputId& input_id) con
MuxMemId mem = edge_mem_ids_[edge];
VTR_ASSERT_SAFE (valid_mem_id(mem));
if (true == edge_inv_mem_[edge]) {
mem_bits[size_t(mem)] = 0;
mem_bits[mem] = false;
} else {
mem_bits[size_t(mem)] = 1;
mem_bits[mem] = true;
}
/* each edge must have 1 fan-out */
VTR_ASSERT_SAFE (1 == edge_sink_nodes_[edge].size());
/* Visit the next node */
next_node = edge_sink_nodes_[edge][0];
/* Get the fan-out node */
MuxNodeId next_node = edge_sink_nodes_[edge][0];
/* If next node is the output node we want, we can finish here */
if (next_node == node_id(output_id)) {
route_success = true;
break;
}
/* Add next node to the queue if not visited yet */
if (false == visited[next_node]) {
visited[next_node] = true;
queue.push_back(next_node);
}
}
/* valid the output */
VTR_ASSERT_SAFE(MUX_OUTPUT_NODE == node_types_[next_node]);
VTR_ASSERT_SAFE(valid_output_id(node_output_ids_[next_node]));
/* Routing must be success! */
VTR_ASSERT(true == route_success);
return mem_bits;
}
/* Find the input node that the memory bits will route an output node to
* This function backward propagate from the output node to an input node
* assuming the memory bits are applied
*/
MuxInputId MuxGraph::find_input_node_driven_by_output_node(const std::map<MuxMemId, bool>& memory_bits,
const MuxOutputId& output_id) const {
/* Ensure that the memory bits fit the size of memory bits in this MUX */
VTR_ASSERT(memory_bits.size() == mem_ids_.size());
/* valid the output */
VTR_ASSERT_SAFE(valid_output_id(output_id));
/* Start from the output node */
/* Mark all the nodes as not visited */
vtr::vector<MuxNodeId, bool> visited(nodes().size(), false);
/* Create a queue for Breadth-First Search */
std::list<MuxNodeId> queue;
/* Mark the output node as visited and enqueue it */
visited[node_id(output_id)] = true;
queue.push_back(node_id(output_id));
/* Record the destination input id */
MuxInputId des_input_id = MuxInputId::INVALID();
while(!queue.empty()) {
/* Dequeue a mux node from queue,
* we will walk through all the fan-in of this node in this loop
*/
MuxNodeId node_to_expand = queue.front();
queue.pop_front();
/* Get all fan-in nodes of the dequeued node
* If the node has not been visited,
* then mark it visited and enqueue it
*/
MuxEdgeId next_edge = MuxEdgeId::INVALID();
for (const MuxEdgeId& edge : node_in_edges_[node_to_expand]) {
/* Configure the mem bits and find the edge that will propagate the signal
* if inv_mem is enabled, it means false to enable this edge
* otherwise, it is true to enable this edge
*/
MuxMemId mem = edge_mem_ids_[edge];
VTR_ASSERT_SAFE (valid_mem_id(mem));
if (edge_inv_mem_[edge] == !memory_bits.at(mem)) {
next_edge = edge;
break;
}
}
/* We must have a valid next edge */
VTR_ASSERT(MuxEdgeId::INVALID() != next_edge);
/* each edge must have 1 fan-out */
VTR_ASSERT_SAFE (1 == edge_src_nodes_[next_edge].size());
/* Get the fan-in node */
MuxNodeId next_node = edge_src_nodes_[next_edge][0];
/* If next node is an input node, we can finish here */
if (true == is_node_input(next_node)) {
des_input_id = input_id(next_node);
break;
}
/* Add next node to the queue if not visited yet */
if (false == visited[next_node]) {
visited[next_node] = true;
queue.push_back(next_node);
}
}
/* Routing must be success! */
VTR_ASSERT(MuxInputId::INVALID() != des_input_id);
return des_input_id;
}
/**************************************************
* Private mutators: basic operations
*************************************************/
@ -1000,7 +1202,7 @@ bool MuxGraph::valid_output_id(const MuxOutputId& output_id) const {
}
bool MuxGraph::valid_level(const size_t& level) const {
return level < num_levels();
return level < num_node_levels();
}
bool MuxGraph::valid_node_lookup() const {

29
vpr7_x2p/vpr/SRC/device/mux_graph.h
View File

@ -27,6 +27,7 @@
#ifndef MUX_GRAPH_H
#define MUX_GRAPH_H
#include <map>
#include "vtr_vector.h"
#include "vtr_range.h"
#include "mux_graph_fwd.h"
@ -62,7 +63,10 @@ class MuxGraph {
std::vector<MuxNodeId> non_input_nodes() const;
edge_range edges() const;
mem_range memories() const;
/* Find the number of levels in terms of the multiplexer */
std::vector<size_t> levels() const;
/* Find the actual number of levels in the graph */
std::vector<size_t> node_levels() const;
public: /* Public accessors: Data query */
/* Find the number of inputs in the MUX graph */
size_t num_inputs() const;
@ -79,6 +83,8 @@ class MuxGraph {
size_t num_memory_bits() const;
/* Find the number of SRAMs at a level in the MUX graph */
size_t num_memory_bits_at_level(const size_t& level) const;
/* Return memory id at level */
std::vector<MuxMemId> memories_at_level(const size_t& level) const;
/* Find the number of nodes at a given level in the MUX graph */
size_t num_nodes_at_level(const size_t& level) const;
/* Find the level of a node */
@ -95,19 +101,38 @@ class MuxGraph {
bool is_edge_use_inv_mem(const MuxEdgeId& edge) const;
/* Find the sizes of each branch of a MUX */
std::vector<size_t> branch_sizes() const;
/* Find the sizes of each branch of a MUX at a given level */
std::vector<size_t> branch_sizes(const size_t& level) const;
/* Generate MUX graphs for its branches */
MuxGraph subgraph(const MuxNodeId& node) const;
std::vector<MuxGraph> build_mux_branch_graphs() const;
/* Get the node id of a given input */
MuxNodeId node_id(const MuxInputId& input_id) const;
/* Get the node id of a given output */
MuxNodeId node_id(const MuxOutputId& output_id) const;
/* Get the node id w.r.t. the node level and node_index at the level */
MuxNodeId node_id(const size_t& node_level, const size_t& node_index_at_level) const;
/* Get the input id of a given node */
MuxInputId input_id(const MuxNodeId& node_id) const;
/* Identify if the node is an input of the MUX */
bool is_node_input(const MuxNodeId& node_id) const;
/* Get the output id of a given node */
MuxOutputId output_id(const MuxNodeId& node_id) const;
/* Decode memory bits based on an input id */
std::vector<size_t> decode_memory_bits(const MuxInputId& input_id) const;
/* Identify if the node is an output of the MUX */
bool is_node_output(const MuxNodeId& node_id) const;
/* Decode memory bits based on an input id and an output id
* This function will start from the input node
* and do a forward propagation until reaching the output node
*/
vtr::vector<MuxMemId, bool> decode_memory_bits(const MuxInputId& input_id,
const MuxOutputId& output_id) const;
/* Find the input node that the memory bits will route an output node to
* This function backward propagate from the output node to an input node
* assuming the memory bits are applied
* Note: This function is mainly used for decoding LUT MUXes
*/
MuxInputId find_input_node_driven_by_output_node(const std::map<MuxMemId, bool>& memory_bits,
const MuxOutputId& output_id) const;
private: /* Private mutators : basic operations */
/* Add a unconfigured node to the MuxGraph */
MuxNodeId add_node(const enum e_mux_graph_node_type& node_type);

4
vpr7_x2p/vpr/SRC/device/mux_library_builder.h
View File

@ -6,6 +6,10 @@
#ifndef MUX_LIBRARY_BUILDER_H
#define MUX_LIBRARY_BUILDER_H
#include "vpr_types.h"
#include "circuit_library.h"
#include "mux_library.h"
MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
t_switch_inf* switches,
const CircuitLibrary& circuit_lib,

106
vpr7_x2p/vpr/SRC/device/mux_utils.cpp
View File

@ -386,3 +386,109 @@ size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib,
return num_config_bits;
}
/**************************************************
* Find the number of shared configuration bits for a CMOS multiplexer
* Currently, all the supported CMOS multiplexers
* do NOT require any shared configuration bits
*************************************************/
static
size_t find_cmos_mux_num_shared_config_bits(const e_sram_orgz& sram_orgz_type) {
size_t num_shared_config_bits = 0;
switch (sram_orgz_type) {
case SPICE_SRAM_MEMORY_BANK:
case SPICE_SRAM_SCAN_CHAIN:
case SPICE_SRAM_STANDALONE:
num_shared_config_bits = 0;
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n",
__FILE__, __LINE__);
exit(1);
}
return num_shared_config_bits;
}
/**************************************************
* Find the number of shared configuration bits for a ReRAM multiplexer
*************************************************/
static
size_t find_rram_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& mux_model,
const MuxGraph& mux_graph,
const e_sram_orgz& sram_orgz_type) {
size_t num_shared_config_bits = 0;
switch (sram_orgz_type) {
case SPICE_SRAM_MEMORY_BANK: {
/* In memory bank, the number of shared configuration bits is
* the sum of largest branch size at each level
*/
for (auto lvl : mux_graph.node_levels()) {
/* Find the maximum branch size:
* Note that branch_sizes() returns a sorted vector
* The last one is the maximum
*/
num_shared_config_bits += mux_graph.branch_sizes(lvl).back();
}
break;
}
case SPICE_SRAM_SCAN_CHAIN:
case SPICE_SRAM_STANDALONE:
/* Currently we DO NOT SUPPORT THESE, given an invalid number */
num_shared_config_bits = size_t(-1);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n",
__FILE__, __LINE__);
exit(1);
}
if (true == circuit_lib.mux_use_local_encoder(mux_model)) {
/* TODO: this is a to-do work for ReRAM-based multiplexers and FPGAs
* The number of states of a local decoder only depends on how many
* memory bits that the multiplexer will have
* This may NOT be correct!!!
* If local encoders are introduced, zero shared configuration bits are required
*/
return 0;
}
return num_shared_config_bits;
}
/**************************************************
* Find the number of shared configuration bits for
* a routing multiplexer
* Two cases are considered here.
* They are placed in different branches (sub-functions)
* in order to be easy in extending to new technology!
*
* Note: currently, shared configuration bits are demanded
* by ReRAM-based multiplexers only
*************************************************/
size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& mux_model,
const MuxGraph& mux_graph,
const e_sram_orgz& sram_orgz_type) {
size_t num_shared_config_bits = size_t(-1);
switch (circuit_lib.design_tech_type(mux_model)) {
case SPICE_MODEL_DESIGN_CMOS:
num_shared_config_bits = find_cmos_mux_num_shared_config_bits(sram_orgz_type);
break;
case SPICE_MODEL_DESIGN_RRAM:
num_shared_config_bits = find_rram_mux_num_shared_config_bits(circuit_lib, mux_model, mux_graph, sram_orgz_type);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n",
__FILE__, __LINE__, circuit_lib.model_name(mux_model).c_str());
exit(1);
}
return num_shared_config_bits;
}

5
vpr7_x2p/vpr/SRC/device/mux_utils.h
View File

@ -46,4 +46,9 @@ size_t find_mux_num_config_bits(const CircuitLibrary& circuit_lib,
const MuxGraph& mux_graph,
const e_sram_orgz& sram_orgz_type);
size_t find_mux_num_shared_config_bits(const CircuitLibrary& circuit_lib,
const CircuitModelId& mux_model,
const MuxGraph& mux_graph,
const e_sram_orgz& sram_orgz_type);
#endif

31
vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context.h
View File

@ -1,31 +0,0 @@
/******************************************************************************
* This file introduces a data structure to store bitstream-related information
******************************************************************************/
#ifndef BITSTREAM_CONTEXT_H
#define BITSTREAM_CONTEXT_H
#include "vtr_vector.h"
#include "bitstream_context_fwd.h"
class BitstreamContext {
private: /* Internal data */
enum e_sram_orgz config_scheme_; /* The type of configuration protocol */
CircuitModelId& sram_model_; /* The memory circuit model used by the Bitstream generation */
size_t num_memory_bits_; /* Number of memory bits */
size_t num_bls_; /* Number of Bit Lines */
size_t num_wls_; /* Number of Word Lines */
size_t num_reserved_bls_; /* Number of reserved Bit Lines, ONLY applicable to RRAM-based FPGA */
size_t num_reserved_wls_; /* Number of reserved Word Lines, ONLY applicable to RRAM-based FPGA */
/* Unique id of a bit in the Bitstream */
vtr::vector<ConfigBitId, ConfigBitId> bit_ids_;
/* Bit line address of a bit in the Bitream: ONLY applicable to memory-decoders */
vtr::vector<ConfigBitId, size_t> bl_addr_;
/* Word line address of a bit in the Bitream: ONLY applicable to memory-decoders */
vtr::vector<ConfigBitId, size_t> wl_addr_;
/* value of a bit in the Bitream */
vtr::vector<ConfigBitId, bool> bit_val_;
};
#endif

18
vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_context_fwd.h
View File

@ -1,18 +0,0 @@
/**************************************************
* This file includes only declarations for
* the data structures for module managers
* Please refer to module_manager.h for more details
*************************************************/
#ifndef MODULE_MANAGER_FWD_H
#define MODULE_MANAGER_FWD_H
#include "vtr_strong_id.h"
/* Strong Ids for ModuleManager */
struct config_bit_id_tag;
typedef vtr::StrongId<config_bit_id_tag> ConfigBitId;
class BitstreamContext;
#endif

184
vpr7_x2p/vpr/SRC/fpga_x2p/base/bitstream_manager.cpp Normal file
View File

@ -0,0 +1,184 @@
/******************************************************************************
* This file includes member functions for data structure BitstreamManager
******************************************************************************/
#include <algorithm>
#include "vtr_assert.h"
#include "bitstream_manager.h"
/**************************************************
* Public Accessors : Aggregates
*************************************************/
/* Find all the configuration bits */
BitstreamManager::config_bit_range BitstreamManager::bits() const {
return vtr::make_range(bit_ids_.begin(), bit_ids_.end());
}
/* Find all the configuration blocks */
BitstreamManager::config_block_range BitstreamManager::blocks() const {
return vtr::make_range(block_ids_.begin(), block_ids_.end());
}
/******************************************************************************
* Public Accessors
******************************************************************************/
bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const {
/* Ensure a valid id */
VTR_ASSERT(true == valid_bit_id(bit_id));
return bit_values_[bit_id];
}
std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
return block_names_[block_id];
}
ConfigBlockId BitstreamManager::block_parent(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
return parent_block_ids_[block_id];
}
std::vector<ConfigBlockId> BitstreamManager::block_children(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
return child_block_ids_[block_id];
}
std::vector<ConfigBitId> BitstreamManager::block_bits(const ConfigBlockId& block_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
return block_bit_ids_[block_id];
}
ConfigBlockId BitstreamManager::bit_parent_block(const ConfigBitId& bit_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_bit_id(bit_id));
return bit_parent_block_ids_[bit_id];
}
size_t BitstreamManager::bit_index_in_parent_block(const ConfigBitId& bit_id) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_bit_id(bit_id));
ConfigBlockId bit_parent_block = bit_parent_block_ids_[bit_id];
VTR_ASSERT(true == valid_block_id(bit_parent_block));
for (size_t index = 0; index < block_bits(bit_parent_block).size(); ++index) {
if (bit_id == block_bits(bit_parent_block)[index]) {
return index;
}
}
/* Not found, return in valid value */
return size_t(-1);
}
/* Find the child block in a bitstream manager with a given name */
ConfigBlockId BitstreamManager::find_child_block(const ConfigBlockId& block_id,
const std::string& child_block_name) const {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block_id));
std::vector<ConfigBlockId> candidates;
for (const ConfigBlockId& child : block_children(block_id)) {
if (0 == child_block_name.compare(block_name(child))) {
candidates.push_back(child);
}
}
/* We should have 0 or 1 candidate! */
VTR_ASSERT(0 == candidates.size() || 1 == candidates.size());
if (0 == candidates.size()) {
/* Not found, return an invalid value */
return ConfigBlockId::INVALID();
}
return candidates[0];
}
/******************************************************************************
* Public Mutators
******************************************************************************/
ConfigBitId BitstreamManager::add_bit(const bool& bit_value) {
ConfigBitId bit = ConfigBitId(bit_ids_.size());
/* Add a new bit, and allocate associated data structures */
bit_ids_.push_back(bit);
bit_values_.push_back(bit_value);
shared_config_bit_values_.emplace_back();
bit_parent_block_ids_.push_back(ConfigBlockId::INVALID());
return bit;
}
ConfigBlockId BitstreamManager::add_block(const std::string& block_name) {
ConfigBlockId block = ConfigBlockId(block_ids_.size());
/* Add a new bit, and allocate associated data structures */
block_ids_.push_back(block);
block_names_.push_back(block_name);
block_bit_ids_.emplace_back();
parent_block_ids_.push_back(ConfigBlockId::INVALID());
child_block_ids_.emplace_back();
return block;
}
void BitstreamManager::add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(parent_block));
VTR_ASSERT(true == valid_block_id(child_block));
/* We should have only a parent block for each block! */
VTR_ASSERT(ConfigBlockId::INVALID() == parent_block_ids_[child_block]);
/* Ensure the child block is not in the list of children of the parent block */
std::vector<ConfigBlockId>::iterator it = std::find(child_block_ids_[parent_block].begin(), child_block_ids_[parent_block].end(), child_block);
VTR_ASSERT(it == child_block_ids_[parent_block].end());
/* Add the child_block to the parent_block */
child_block_ids_[parent_block].push_back(child_block);
/* Register the block in the parent of the block */
parent_block_ids_[child_block] = parent_block;
}
void BitstreamManager::add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
VTR_ASSERT(true == valid_bit_id(bit));
/* We should have only a parent block for each bit! */
VTR_ASSERT(ConfigBlockId::INVALID() == bit_parent_block_ids_[bit]);
/* Add the bit to the block */
block_bit_ids_[block].push_back(bit);
/* Register the block in the parent of the bit */
bit_parent_block_ids_[bit] = block;
}
void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_bit_id(bit));
shared_config_bit_values_[bit] = shared_config_bits;
}
/******************************************************************************
* Public Validators
******************************************************************************/
bool BitstreamManager::valid_bit_id(const ConfigBitId& bit_id) const {
return (size_t(bit_id) < bit_ids_.size()) && (bit_id == bit_ids_[bit_id]);
}
bool BitstreamManager::valid_block_id(const ConfigBlockId& block_id) const {
return (size_t(block_id) < block_ids_.size()) && (block_id == block_ids_[block_id]);
}

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/******************************************************************************
* This file introduces a data structure to store bitstream-related information
*
* General concept
* ---------------
* The idea is to create a unified data structure that stores all the configuration bits
* with proper annotation to which modules in FPGA fabric it belongs to.
* 1. It can be easily organized in fabric-dependent representation
* (generate a sequence of bitstream which exactly fit the configuration protocol of FPGA fabric)
* 2. Or it can be easily organized in fabric-independent representation (think about XML file)
*
* Cross-reference
* ---------------
* May be used only when you want to bind the bitstream to a specific FPGA fabric!
* If you do so, please make sure the block name is exactly same as the instance name
* of a child module in ModuleManager!!!
* The configurable modules/instances in module manager are arranged
* in the sequence to fit different configuration protocol.
* By using the link between ModuleManager and BitstreamManager,
* we can build a sequence of configuration bits to fit different configuration protocols.
*
* +------------------+ +-----------------+
* | | block_name == instance_name | |
* | BitstreamManager |-------------------------------->| ModuleManager |
* | | | |
* +------------------+ +-----------------+
*
* Restrictions:
* 1. Each block inside BitstreamManager should have only 1 parent block
* and multiple child block
* 2. Each bit inside BitstreamManager should have only 1 parent block
*
******************************************************************************/
#ifndef BITSTREAM_MANAGER_H
#define BITSTREAM_MANAGER_H
#include <vector>
#include <map>
#include "vtr_vector.h"
#include "bitstream_manager_fwd.h"
class BitstreamManager {
public: /* Types and ranges */
typedef vtr::vector<ConfigBitId, ConfigBitId>::const_iterator config_bit_iterator;
typedef vtr::vector<ConfigBlockId, ConfigBlockId>::const_iterator config_block_iterator;
typedef vtr::Range<config_bit_iterator> config_bit_range;
typedef vtr::Range<config_block_iterator> config_block_range;
public: /* Public aggregators */
/* Find all the configuration bits */
config_bit_range bits() const;
config_block_range blocks() const;
public: /* Public Accessors */
/* Find the value of bitstream */
bool bit_value(const ConfigBitId& bit_id) const;
/* Find a name of a block */
std::string block_name(const ConfigBlockId& block_id) const;
/* Find the parent of a block */
ConfigBlockId block_parent(const ConfigBlockId& block_id) const;
/* Find the children of a block */
std::vector<ConfigBlockId> block_children(const ConfigBlockId& block_id) const;
/* Find all the bits that belong to a block */
std::vector<ConfigBitId> block_bits(const ConfigBlockId& block_id) const;
/* Find the parent block of a bit */
ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const;
/* Find the index of a configuration bit in its parent block */
size_t bit_index_in_parent_block(const ConfigBitId& bit_id) const;
/* Find the child block in a bitstream manager with a given name */
ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const;
public: /* Public Mutators */
/* Add a new configuration bit to the bitstream manager */
ConfigBitId add_bit(const bool& bit_value);
/* Add a new block of configuration bits to the bitstream manager */
ConfigBlockId add_block(const std::string& block_name);
/* Set a block as a child block of another */
void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block);
/* Add a configuration bit to a block */
void add_bit_to_block(const ConfigBlockId& block, const ConfigBitId& bit);
/* Add share configuration bits to a configuration bit */
void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits);
public: /* Public Validators */
bool valid_bit_id(const ConfigBitId& bit_id) const;
bool valid_block_id(const ConfigBlockId& block_id) const;
private: /* Internal data */
/* Unique id of a block of bits in the Bitstream */
vtr::vector<ConfigBlockId, ConfigBlockId> block_ids_;
vtr::vector<ConfigBlockId, std::vector<ConfigBitId>> block_bit_ids_;
/* Back-annotation for the bits */
/* Parent block of a bit in the Bitstream
* For each bit, the block name can be designed to be same as the instance name in a module
* to reflect its position in the module tree (ModuleManager)
* Note that the blocks here all unique, unlike ModuleManager where modules can be instanciated
* Therefore, this block graph can be considered as a flattened graph of ModuleGraph
*/
vtr::vector<ConfigBlockId, std::string> block_names_;
vtr::vector<ConfigBlockId, ConfigBlockId> parent_block_ids_;
vtr::vector<ConfigBlockId, std::vector<ConfigBlockId>> child_block_ids_;
/* Unique id of a bit in the Bitstream */
vtr::vector<ConfigBitId, ConfigBitId> bit_ids_;
vtr::vector<ConfigBitId, ConfigBlockId> bit_parent_block_ids_;
/* value of a bit in the Bitstream */
vtr::vector<ConfigBitId, bool> bit_values_;
/* value of a shared configuration bits in the Bitstream */
vtr::vector<ConfigBitId, std::vector<bool>> shared_config_bit_values_;
};
#endif

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