riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Architecture] Bug fix in Verilog netlist for scan-chain DFF

This commit is contained in:
tangxifan 2020-09-24 17:41:03 -06:00
parent 7494556316
commit 3e7c88eac8
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga_flow/VerilogNetlists/dff.v
View File

@ -213,7 +213,7 @@ module DFFSRQ (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
@ -294,7 +294,7 @@ module SDFFSRQ (
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q, // Q output
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;

6
openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml
View File

@ -155,7 +155,7 @@
<port type="bl" prefix="bl" lib_name="D" size="1"/>
<port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="QB" size="1"/>
<port type="output" prefix="Qb" lib_name="QN" size="1"/>
<port type="input" prefix="SE" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="SI" lib_name="SI" size="1" is_global="true" default_val="0"/>
</circuit_model>
@ -164,13 +164,13 @@
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="DFF_EN" default_val="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="SDFFSR" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="frame_based" circuit_model_name="DFF_EN"/>
<organization type="frame_based" circuit_model_name="SDFFSR"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>