[Cleanup] Removed deadcode
This commit is contained in:
parent
f124c79e6b
commit
df4a397470
26
openfpga.sh
26
openfpga.sh
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@ -29,6 +29,10 @@ run-task () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
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}
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clean-run () {
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rm -rf ./openfpga_flow/**/run???
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}
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run-modelsim () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_modelsim.py "$@"
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}
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@ -48,6 +52,21 @@ goto-root () {
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cd $OPENFPGA_PATH
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}
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# Run regression test locally
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run-regression-local () {
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cd ${OPENFPGA_PATH}
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bash .github/workflows/*reg_test.sh
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}
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# Run regression test locally
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run-regression-local-docker () {
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cd ${OPENFPGA_PATH}
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docker run \
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-v $(pwd)/openfpga_flow:/opt/openfpga/ \
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-v $(pwd)/.github:/opt/openfpga/ \
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ghcr.io/lnis-uofu/openfpga-master:latest "bash .github/workflows/*reg_test.sh"
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}
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# Changes directory to task directory [goto_task <task_name> <run_num[default 0]>]
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goto-task () {
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if [ -z $1 ]; then
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@ -55,6 +74,7 @@ goto-task () {
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return
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fi
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goto_path=$OPENFPGA_TASK_PATH/$1
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# Selects the run directory
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run_num=""
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if [ ! -d $goto_path ]; then echo "Task directory not found"; return; fi
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if [[ "$2" =~ '^[0-9]+$' ]] ; then
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@ -67,6 +87,12 @@ goto-task () {
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echo "Switching current dirctory to" $goto_path/$run_num
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cd $goto_path/$run_num
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fi
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# Selects benchmark directory
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select benchRun in $(ls -d **/arch | sed "s/\/arch//" | head -n 20)
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do
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[ -d ${benchRun} ] && cd ${benchRun}
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break
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done
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}
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# Clears enviroment variables and fucntions
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@ -14,7 +14,7 @@ iverilog_path = iverilog
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include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists
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[FLOW_SCRIPT_CONFIG]
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valid_flows = standard,vpr_blif,vtr,vtr_standard,yosys_vpr
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valid_flows = vpr_blif,yosys_vpr
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[DEFAULT_PARSE_RESULT_VPR]
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# parser format <name of variable> = <regex string>, <lambda function/type>
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@ -11,6 +11,7 @@ import os
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import sys
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import shutil
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import time
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import traceback
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from datetime import timedelta
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import shlex
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import glob
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@ -84,6 +85,9 @@ parser.add_argument('--run_dir', type=str,
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default=os.path.join(openfpga_base_dir, 'tmp'),
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help="Directory to store intermidiate file & final results")
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parser.add_argument('--openfpga_shell_template', type=str,
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default=os.path.join("openfpga_flow",
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"openfpga_shell_scripts",
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"example_script.openfpga"),
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help="Sample openfpga shell script")
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parser.add_argument('--openfpga_arch_file', type=str,
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help="Openfpga architecture file for shell")
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@ -264,11 +268,8 @@ def main():
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# run_abc_vtr()
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# if (args.fpga_flow == "vtr_standard"):
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# run_abc_for_standarad()
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if args.openfpga_shell_template:
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logger.info("Runing OpenFPGA Shell Engine ")
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run_openfpga_shell()
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else:
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run_vpr()
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logger.info("Runing OpenFPGA Shell Engine ")
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run_openfpga_shell()
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if args.end_flow_with_test:
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run_netlists_verification()
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@ -328,10 +329,21 @@ def read_script_config():
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def validate_command_line_arguments():
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"""
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TODO :
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This funtion validates all supplied paramters
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"""
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'''
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This function validate the command line arguments
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FLOW_SCRIPT_CONFIG->valid_flows :
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Key is used to validate if the request flow is supported by the script
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CMD_ARGUMENT_DEPENDANCY :
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Validates the dependencies of the command arguments
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Checks the following file exists and replaces them with an absolute path
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- All architecture files
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- Benchmark files
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- Power tech files
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- Run directory
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- Activity file
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- Base verilog file
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'''
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logger.info("Validating commnad line arguments")
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if args.debug:
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@ -351,10 +363,17 @@ def validate_command_line_arguments():
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clean_up_and_exit("'%s' argument depends on (%s) argumets" %
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(eacharg, ", ".join(dependent).replace("|", " or ")))
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# Filter provided architecture files
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# Check if architecrue files exists
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args.arch_file = os.path.abspath(args.arch_file)
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if not os.path.isfile(args.arch_file):
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clean_up_and_exit("Architecture file not found. -%s", args.arch_file)
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clean_up_and_exit(
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"VPR architecture file not found. -%s",
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args.arch_file)
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args.openfpga_arch_file = os.path.abspath(args.openfpga_arch_file)
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if not os.path.isfile(args.openfpga_arch_file):
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clean_up_and_exit(
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"OpenFPGA architecture file not found. -%s",
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args.openfpga_arch_file)
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# Filter provided benchmark files
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for index, everyinput in enumerate(args.benchmark_files):
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@ -384,18 +403,6 @@ def validate_command_line_arguments():
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args.base_verilog = os.path.abspath(args.base_verilog)
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def ask_user_quetion(condition, question):
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if condition:
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reply = str(input(question+' (y/n): ')).lower().strip()
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if reply[:1] in ['n', 'no']:
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return False
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elif reply[:1] in ['y', 'yes']:
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return True
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else:
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return ask_user_quetion(question, condition)
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return True
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def prepare_run_directory(run_dir):
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"""
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Prepares run directory to run
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@ -406,13 +413,7 @@ def prepare_run_directory(run_dir):
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logger.info("Run directory : %s" % run_dir)
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if os.path.isdir(run_dir):
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no_of_files = len(next(os.walk(run_dir))[2])
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if not ask_user_quetion((no_of_files > 100),
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("[run_dir:%s] already exist and contains %d " +
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"files script will remove all the file, " +
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"continue? ") % (run_dir, no_of_files)):
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clean_up_and_exit("Aborted by user")
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else:
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shutil.rmtree(run_dir)
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shutil.rmtree(run_dir)
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os.makedirs(run_dir)
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# Clean run_dir is created change working directory
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os.chdir(run_dir)
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@ -492,22 +493,9 @@ def run_yosys_with_abc():
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tmpl = Template(open(yosys_template, encoding='utf-8').read())
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with open("yosys.ys", 'w') as archfile:
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archfile.write(tmpl.safe_substitute(ys_params))
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try:
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with open('yosys_output.txt', 'w+') as output:
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process = subprocess.run([cad_tools["yosys_path"], 'yosys.ys'],
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check=True,
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE,
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universal_newlines=True)
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output.write(process.stdout)
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if process.returncode:
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logger.info("Yosys failed with returncode %d",
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process.returncode)
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raise subprocess.CalledProcessError(0, command)
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except:
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logger.exception("Failed to run yosys")
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clean_up_and_exit("")
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logger.info("Yosys output is written in file yosys_output.txt")
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run_command("Run yosys", "yosys_output.log",
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[cad_tools["yosys_path"], 'yosys.ys'])
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def run_odin2():
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@ -627,72 +615,6 @@ def collect_files_for_vpr():
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shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
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def run_vpr():
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ExecTime["VPRStart"] = time.time()
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# Format the BLIF File
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cmd = r"mv %s.blif %s.blif.bak && cat %s.blif.bak" % (
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args.top_module,
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args.top_module,
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args.top_module)
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cmd += r"| sed 's/$/./' | fold -s -w80 "
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cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$//'"
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cmd += " > %s.blif" % args.top_module
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os.system(cmd)
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if not args.fix_route_chan_width:
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# Run Standard VPR Flow
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min_channel_width = run_standard_vpr(
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args.top_module+".blif",
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-1,
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args.top_module+"_min_chan_width_vpr.txt")
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logger.info("Standard VPR flow routed with minimum %d Channels" %
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min_channel_width)
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# Minimum routing channel width
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if (args.min_route_chan_width):
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min_channel_width *= args.min_route_chan_width
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min_channel_width = int(min_channel_width)
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min_channel_width += 1 if (min_channel_width % 2) else 0
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logger.info(("Trying to route using %d channels" % min_channel_width) +
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" (Slack of %d%%)" % ((args.min_route_chan_width-1)*100))
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while(1):
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res = run_standard_vpr(args.top_module+".blif",
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int(min_channel_width),
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args.top_module+"_reroute_vpr.txt",
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route_only=True)
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if res:
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logger.info("Routing with channel width=%d successful" %
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min_channel_width)
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break
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elif args.max_route_width_retry < (min_channel_width-2):
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clean_up_and_exit("Failed to route within maximum " +
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"iteration of channel width")
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else:
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logger.info("Unable to route using channel width %d" %
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min_channel_width)
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min_channel_width += 2
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extract_vpr_stats(args.top_module+"_reroute_vpr.txt")
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# Fixed routing channel width
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elif args.fix_route_chan_width:
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min_channel_width = run_standard_vpr(
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args.top_module+".blif",
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args.fix_route_chan_width,
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args.top_module+"_fr_chan_width_vpr.txt")
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logger.info("Fixed routing channel successfully routed with %d width" %
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min_channel_width)
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extract_vpr_stats(args.top_module+"_fr_chan_width_vpr.txt")
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else:
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extract_vpr_stats(args.top_module+"_min_chan_width_vpr.txt")
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if args.power:
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extract_vpr_stats(logfile=args.top_module+".power",
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r_filename="vpr_power_stat",
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parse_section="power")
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ExecTime["VPREnd"] = time.time()
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def run_openfpga_shell():
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ExecTime["VPRStart"] = time.time()
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# bench_blif, fixed_chan_width, logfile, route_only=False
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@ -702,8 +624,6 @@ def run_openfpga_shell():
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path_variables = script_env_vars["PATH"]
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path_variables["VPR_ARCH_FILE"] = args.arch_file
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path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
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# path_variables["OPENFPGA_SIM_SETTING_FILE"] = args.openfpga_sim_setting_file
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# path_variables["EXTERNAL_FABRIC_KEY_FILE"] = args.external_fabric_key_file
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path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
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path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
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path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
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@ -715,169 +635,13 @@ def run_openfpga_shell():
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with open(args.top_module+"_run.openfpga", 'w', encoding='utf-8') as archfile:
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archfile.write(tmpl.safe_substitute(path_variables))
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command = [cad_tools["openfpga_shell_path"], "-f",
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command = [cad_tools["openfpga_shell_path"], "-batch", "-f",
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args.top_module+"_run.openfpga"]
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run_command("OpenFPGA Shell Run", "openfpgashell.log", command)
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ExecTime["VPREnd"] = time.time()
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extract_vpr_stats("vpr_stdout.log")
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def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
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command = [cad_tools["vpr_path"],
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args.arch_file,
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bench_blif,
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"--net_file", args.top_module+"_vpr.net",
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"--place_file", args.top_module+"_vpr.place",
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"--route_file", args.top_module+"_vpr.route",
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"--full_stats", "on",
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"--activity_file", args.top_module+"_ace_out.act",
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]
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if not args.disp:
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command += ["--disp", "off"]
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else:
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command += ["--disp", "on"]
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if route_only:
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command += ["--route"]
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# Power options
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if args.power:
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command += ["--power",
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"--tech_properties", args.power_tech]
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# packer options
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if args.vpr_timing_pack_off:
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command += ["--timing_driven_clustering", "off"]
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# channel width option
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if fixed_chan_width >= 0:
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command += ["--route_chan_width", "%d" % fixed_chan_width]
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if args.vpr_use_tileable_route_chan_width:
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command += ["--use_tileable_route_chan_width"]
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if args.vpr_fpga_x2p_compact_routing_hierarchy:
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command += ["--fpga_x2p_compact_routing_hierarchy"]
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# FPGA_Spice Options
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if (args.vpr_fpga_spice):
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command += ["--fpga_spice"]
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if args.vpr_fpga_x2p_signal_density_weight:
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command += ["--fpga_x2p_signal_density_weight",
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args.vpr_fpga_x2p_signal_density_weight]
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if args.vpr_fpga_x2p_sim_window_size:
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command += ["--fpga_x2p_sim_window_size",
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args.vpr_fpga_x2p_sim_window_size]
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if args.vpr_fpga_spice_sim_mt_num:
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command += ["--fpga_spice_sim_mt_num",
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args.vpr_fpga_spice_sim_mt_num]
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if args.vpr_fpga_spice_simulator_path:
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command += ["--fpga_spice_simulator_path",
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args.vpr_fpga_spice_simulator_path]
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if args.vpr_fpga_spice_print_component_tb:
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command += ["--fpga_spice_print_lut_testbench",
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"--fpga_spice_print_hardlogic_testbench",
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"--fpga_spice_print_pb_mux_testbench",
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"--fpga_spice_print_cb_mux_testbench",
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"--fpga_spice_print_sb_mux_testbench"
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]
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if args.vpr_fpga_spice_print_grid_tb:
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command += ["--fpga_spice_print_grid_testbench",
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"--fpga_spice_print_cb_testbench",
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"--fpga_spice_print_sb_testbench"
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]
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if args.vpr_fpga_spice_print_top_testbench:
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command += ["--fpga_spice_print_top_testbench"]
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if args.vpr_fpga_spice_leakage_only:
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command += ["--fpga_spice_leakage_only"]
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if args.vpr_fpga_spice_parasitic_net_estimation_off:
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command += ["--fpga_spice_parasitic_net_estimation", "off"]
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if args.vpr_fpga_spice_testbench_load_extraction_off:
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command += ["--fpga_spice_testbench_load_extraction", "off"]
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# FPGA Verilog options
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if args.vpr_fpga_verilog:
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command += ["--fpga_verilog"]
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if args.vpr_fpga_verilog_dir:
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command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir]
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if args.vpr_fpga_verilog_print_top_tb:
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command += ["--fpga_verilog_print_top_testbench"]
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if args.vpr_fpga_verilog_print_input_blif_tb:
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command += ["--fpga_verilog_print_input_blif_testbench"]
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if args.vpr_fpga_verilog_print_autocheck_top_testbench:
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command += ["--fpga_verilog_print_autocheck_top_testbench",
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# args.vpr_fpga_verilog_print_autocheck_top_testbench]
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os.path.join(args.run_dir, args.top_module+"_output_verilog.v")]
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if args.vpr_fpga_verilog_include_timing:
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command += ["--fpga_verilog_include_timing"]
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if args.vpr_fpga_verilog_explicit_mapping:
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command += ["--fpga_verilog_explicit_mapping"]
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if args.vpr_fpga_x2p_duplicate_grid_pin:
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command += ["--fpga_x2p_duplicate_grid_pin"]
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if args.vpr_fpga_verilog_include_signal_init:
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command += ["--fpga_verilog_include_signal_init"]
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if args.vpr_fpga_verilog_formal_verification_top_netlist:
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command += ["--fpga_verilog_print_formal_verification_top_netlist"]
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if args.vpr_fpga_verilog_print_simulation_ini:
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command += ["--fpga_verilog_print_simulation_ini"]
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if args.vpr_fpga_verilog_include_icarus_simulator:
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command += ["--fpga_verilog_include_icarus_simulator"]
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if args.vpr_fpga_verilog_print_report_timing_tcl:
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command += ["--fpga_verilog_print_report_timing_tcl"]
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if args.vpr_fpga_verilog_report_timing_rpt_path:
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command += ["--fpga_verilog_report_timing_rpt_path",
|
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args.vpr_fpga_verilog_report_timing_rpt_path]
|
||||
if args.vpr_fpga_verilog_print_sdc_pnr:
|
||||
command += ["--fpga_verilog_print_sdc_pnr"]
|
||||
if args.vpr_fpga_verilog_print_user_defined_template:
|
||||
command += ["--fpga_verilog_print_user_defined_template"]
|
||||
if args.vpr_fpga_verilog_print_sdc_analysis:
|
||||
command += ["--fpga_verilog_print_sdc_analysis"]
|
||||
|
||||
# FPGA Bitstream Genration options
|
||||
if args.vpr_fpga_verilog_print_sdc_analysis:
|
||||
command += ["--fpga_bitstream_generator"]
|
||||
|
||||
if args.vpr_fpga_x2p_rename_illegal_port or \
|
||||
args.vpr_fpga_spice or \
|
||||
args.vpr_fpga_verilog:
|
||||
command += ["--fpga_x2p_rename_illegal_port"]
|
||||
|
||||
# Other VPR options
|
||||
if args.vpr_place_clb_pin_remap:
|
||||
command += ["--place_clb_pin_remap"]
|
||||
if args.vpr_route_breadthfirst:
|
||||
command += ["--router_algorithm", "breadth_first"]
|
||||
if args.vpr_max_router_iteration:
|
||||
command += ["--max_router_iterations", args.vpr_max_router_iteration]
|
||||
|
||||
chan_width = None
|
||||
try:
|
||||
logger.debug("Running VPR : " + " ".join(command))
|
||||
with open(logfile, 'w+') as output:
|
||||
output.write(" ".join(command)+"\n")
|
||||
process = subprocess.run(command,
|
||||
check=True,
|
||||
stdout=subprocess.PIPE,
|
||||
stderr=subprocess.PIPE,
|
||||
universal_newlines=True)
|
||||
for line in process.stdout.split('\n'):
|
||||
if "Best routing" in line:
|
||||
chan_width = int(re.search(
|
||||
r"channel width factor of ([0-9]+)", line).group(1))
|
||||
if "Circuit successfully routed" in line:
|
||||
chan_width = int(re.search(
|
||||
r"a channel width factor of ([0-9]+)", line).group(1))
|
||||
output.write(process.stdout)
|
||||
if process.returncode:
|
||||
logger.info("Standard VPR run failed with returncode %d",
|
||||
process.returncode)
|
||||
raise subprocess.CalledProcessError(0, command)
|
||||
except (Exception, subprocess.CalledProcessError) as e:
|
||||
logger.exception("Failed to run VPR")
|
||||
filter_failed_process_output(e.output)
|
||||
clean_up_and_exit("")
|
||||
logger.info("VPR output is written in file %s" % logfile)
|
||||
return chan_width
|
||||
|
||||
|
||||
def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
|
||||
section = "DEFAULT_PARSE_RESULT_POWER" if parse_section == "power" \
|
||||
else "DEFAULT_PARSE_RESULT_VPR"
|
||||
|
@ -927,7 +691,7 @@ def run_rewrite_verilog():
|
|||
"write_verilog %s" % args.top_module+"_output_verilog.v"
|
||||
]
|
||||
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
|
||||
run_command("Yosys", "yosys_output.txt", command)
|
||||
run_command("Yosys", "yosys_rewrite.log", command)
|
||||
|
||||
|
||||
def run_netlists_verification(exit_if_fail=True):
|
||||
|
@ -972,29 +736,46 @@ def run_netlists_verification(exit_if_fail=True):
|
|||
|
||||
def run_command(taskname, logfile, command, exit_if_fail=True):
|
||||
logger.info("Launching %s " % taskname)
|
||||
with open(logfile, 'w+') as output:
|
||||
with open(logfile, 'w') as output:
|
||||
try:
|
||||
output.write(" ".join(command)+"\n")
|
||||
process = subprocess.run(command,
|
||||
check=True,
|
||||
stdout=subprocess.PIPE,
|
||||
stderr=subprocess.PIPE,
|
||||
universal_newlines=True)
|
||||
output.write(process.stdout)
|
||||
output.write(process.stderr)
|
||||
output.write(str(process.returncode))
|
||||
if "openfpgashell" in logfile:
|
||||
filter_openfpga_output(process.stdout)
|
||||
if process.returncode:
|
||||
logger.error("%s run failed with returncode %d" %
|
||||
(taskname, process.returncode))
|
||||
except (Exception, subprocess.CalledProcessError) as e:
|
||||
logger.exception("failed to execute %s" % taskname)
|
||||
filter_failed_process_output(e.output)
|
||||
output.write(e.output)
|
||||
logger.error("command %s" % " ".join(command))
|
||||
filter_failed_process_output(process.stderr)
|
||||
if exit_if_fail:
|
||||
clean_up_and_exit("Failed to run %s task" % taskname)
|
||||
except Exception:
|
||||
logger.exception("%s failed to execute" % (taskname))
|
||||
traceback.print_exc(file=output)
|
||||
if exit_if_fail:
|
||||
clean_up_and_exit("Failed to run %s task" % taskname)
|
||||
return None
|
||||
logger.info("%s is written in file %s" % (taskname, logfile))
|
||||
return process.stdout
|
||||
|
||||
|
||||
def filter_openfpga_output(vpr_output):
|
||||
stdout = iter(vpr_output.split("\n"))
|
||||
try:
|
||||
for i in range(50):
|
||||
if "Version:" in next(stdout):
|
||||
logger.info("OpenFPGAShell %s %s" %
|
||||
(next(stdout), next(stdout)))
|
||||
break
|
||||
except StopIteration:
|
||||
pass
|
||||
|
||||
|
||||
def filter_failed_process_output(vpr_output):
|
||||
for line in vpr_output.split("\n"):
|
||||
if "error" in line.lower():
|
||||
|
|
|
@ -26,6 +26,8 @@ import pprint
|
|||
from importlib import util
|
||||
from collections import OrderedDict
|
||||
|
||||
if util.find_spec("coloredlogs"):
|
||||
import coloredlogs
|
||||
if util.find_spec("humanize"):
|
||||
import humanize
|
||||
|
||||
|
@ -35,8 +37,13 @@ if sys.version_info[0] < 3:
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configure logging system
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
logging.basicConfig(level=logging.INFO, stream=sys.stdout,
|
||||
format='%(levelname)s (%(threadName)15s) - %(message)s')
|
||||
LOG_FORMAT = "%(levelname)5s (%(threadName)15s) - %(message)s"
|
||||
if util.find_spec("coloredlogs"):
|
||||
coloredlogs.install(level='INFO', stream=sys.stdout,
|
||||
fmt=LOG_FORMAT)
|
||||
else:
|
||||
logging.basicConfig(level=logging.INFO, stream=sys.stdout,
|
||||
format=LOG_FORMAT)
|
||||
logger = logging.getLogger('OpenFPGA_Task_logs')
|
||||
|
||||
|
||||
|
|
|
@ -1,2 +1,3 @@
|
|||
envyaml==1.0.201125
|
||||
humanize==3.1.0
|
||||
humanize==3.1.0
|
||||
coloredlogs==9.1
|
Loading…
Reference in New Issue