Fixed parameter ys_rewrite_params name bug
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@ -711,7 +711,7 @@ def run_rewrite_verilog():
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ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx + 1]
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tmpl = Template(open(args.ys_rewrite_tmpl, encoding='utf-8').read())
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with open("yosys_rewrite.ys", 'w') as archfile:
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archfile.write(tmpl.safe_substitute(ys_params))
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archfile.write(tmpl.safe_substitute(ys_rewrite_params))
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run_command("Run yosys", "yosys_rewrite_output.log",
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[cad_tools["yosys_path"], 'yosys_rewrite.ys'])
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