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[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr

This commit is contained in:
tangxifan 2021-03-10 13:36:11 -07:00
parent 5d46537b5b
commit 035043d0d8
1 changed files with 6 additions and 7 deletions
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13
openfpga_flow/scripts/run_fpga_task.py
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@ -279,13 +279,12 @@ def generate_each_task_actions(taskname):
"for vpr_blif flow")
CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act")
# Allow user to specify a post-synthesis verilog file for simulation usage
# Check if base verilog file exists
if not SynthSection.get(bech_name+"_verilog"):
clean_up_and_exit("Missing argument %s for vpr_blif flow" %
(bech_name+"_verilog"))
CurrBenchPara["verilog_file"] = SynthSection.get(
bech_name+"_verilog")
# Check if base verilog file exists
if not SynthSection.get(bech_name+"_verilog"):
clean_up_and_exit("Missing argument %s for vpr_blif flow" %
(bech_name+"_verilog"))
CurrBenchPara["verilog_file"] = SynthSection.get(
bech_name+"_verilog")
# Add script parameter list in current benchmark
ScriptSections = [x for x in TaskFileSections if "SCRIPT_PARAM" in x]