From 035043d0d8fb2f1458b4d680af1ce2d3571d8e7f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Mar 2021 13:36:11 -0700 Subject: [PATCH] [Script] Revert to the state that post synthesis verilog is not required for yosys_vpr --- openfpga_flow/scripts/run_fpga_task.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 9f93daa82..e8543a402 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -279,13 +279,12 @@ def generate_each_task_actions(taskname): "for vpr_blif flow") CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") - # Allow user to specify a post-synthesis verilog file for simulation usage - # Check if base verilog file exists - if not SynthSection.get(bech_name+"_verilog"): - clean_up_and_exit("Missing argument %s for vpr_blif flow" % - (bech_name+"_verilog")) - CurrBenchPara["verilog_file"] = SynthSection.get( - bech_name+"_verilog") + # Check if base verilog file exists + if not SynthSection.get(bech_name+"_verilog"): + clean_up_and_exit("Missing argument %s for vpr_blif flow" % + (bech_name+"_verilog")) + CurrBenchPara["verilog_file"] = SynthSection.get( + bech_name+"_verilog") # Add script parameter list in current benchmark ScriptSections = [x for x in TaskFileSections if "SCRIPT_PARAM" in x]