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[Test] Add test case for sdc controller

This commit is contained in:
tangxifan 2021-02-22 15:02:14 -07:00
parent c7a9a4e896
commit 4803b0ce42
4 changed files with 14 additions and 9 deletions
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1
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
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@ -36,5 +36,6 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter12
[SYNTHESIS_PARAM]
bench0_top = counter120bitx5
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

1
openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml
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@ -5,5 +5,6 @@
-->
<set_io pin="clk[0]" net="wb_clk_i"/>
<set_io pin="clk[1]" net="sd_clk_i_pad"/>
<set_io pin="clk[2]" net="sd_clk_o_pad"/>
</pin_constraints>

2
openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml
View File

@ -8,7 +8,7 @@
-->
<pin_constraint pb_type="clb" pin="clk[0]" net="wb_clk_i"/>
<pin_constraint pb_type="clb" pin="clk[1]" net="sd_clk_i_pad"/>
<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[2]" net="sd_clk_o_pad"/>
<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[4]" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk[5]" net="OPEN"/>

19
openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
View File

@ -12,21 +12,20 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 2*60
# Due to the limitation in ACE2 which cannot output .blif files
# with correct multi-clock assignments to .latch lines
# We have to use the vpr_blif flow where the .blif is modified
# based on yosys outputs with correct clock assignment!
# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
#fpga_flow=vpr_blif
# Runtime is around 15 minutes
# But it can be efficiently reduced by improving synthesis script
# (See detailed comments in Synthesis parameter section)
timeout_each_job = 15*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml
openfpga_vpr_route_chan_width=200
openfpga_vpr_device_layout=32x32
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.xml
@ -36,5 +35,9 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_contr
[SYNTHESIS_PARAM]
bench0_top = sdc_controller
# Use standard script for now because QL synthesis recipe generates $DFF_PP model
# Also current synthesis recipe does not support FIFO, BRAM and multiplier
# which causes runtime to be long
#bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]