tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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tangxifan
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0c4904065f
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f9fcc6b471
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@ -0,0 +1,61 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --file fabric_indepenent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ./SDC
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -8,7 +8,7 @@
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[GENERAL]
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run_engine=openfpga_shell
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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@ -21,27 +21,30 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
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[BENCHMARKS]
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#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
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#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
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#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
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## VPR remove dangling PIs and POs which are in act file. Then VPR errors out by saying these PI/PO should not exist in act file
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##bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
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#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
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#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
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#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
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#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
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#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
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#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
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#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
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#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
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#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
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#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
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bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
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#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
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#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
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#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
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#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
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#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
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# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
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bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
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# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
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bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
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bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
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bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
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# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file
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bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
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bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
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bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
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bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
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bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
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bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
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bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
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# Passed
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#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
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bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
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bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
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bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
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bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
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bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
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[SYNTHESIS_PARAM]
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# Benchmark alu4
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