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fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture

This commit is contained in:
tangxifan 2020-07-15 17:52:41 -06:00
parent c26c268dcd
commit eb070694b5
3 changed files with 9 additions and 8 deletions
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9
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1154,17 +1154,18 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
/* Attention: when the fast configuration is enabled, we will start from the first bit '1'
* This requires a reset signal (as we forced in the first clock cycle)
*/
bool first_bit_one = false;
bool start_config = false;
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
first_bit_one = true;
if ( (false == start_config)
&& (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) {
start_config = true;
}
/* In fast configuration mode, we do not output anything
* until we have to (the first bit '1' detected)
*/
if ( (true == fast_configuration)
&& (false == first_bit_one)) {
&& (false == start_config)) {
continue;
}

6
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -242,7 +242,7 @@
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
@ -277,7 +277,7 @@
<pb_type name="clb_spypad.fle" physical_mode_name="physical"/>
<!-- Binding regular FLEs -->
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
<pb_type name="clb_spypad.fle[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="00"/>
<pb_type name="clb_spypad.fle[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb_spypad.fle[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->
@ -310,7 +310,7 @@
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb_spypad.fle_spypad" physical_mode_name="physical"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="11"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.frac_lut6" circuit_model_name="frac_lut6_spypad" mode_bits="00"/>
<pb_type name="clb_spypad.fle_spypad[physical].ff_phy" circuit_model_name="scan_chain_ff"/>
<pb_type name="clb_spypad.fle_spypad[physical].frac_logic.adder_phy" circuit_model_name="adder"/>
<!-- Binding operating pb_type to physical pb_type -->

2
openfpga_flow/tasks/spypad/config/task.conf
View File

@ -8,7 +8,7 @@
[GENERAL]
run_engine=openfpga_shell
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false