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default to ns for time unit -- synopsys dc whines

This commit is contained in:
Nachiket Kapre 2021-02-09 17:04:52 -05:00
parent 87c69460df
commit 6bb2e29f17
2 changed files with 3 additions and 3 deletions
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2
openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
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@ -59,7 +59,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
write_pnr_sdc --time-unit ns --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc

4
openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf
View File

@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=10
openfpga_vpr_device_layout=auto
openfpga_vpr_route_chan_width=20
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml