From 6bb2e29f17f1c62fe2e0c1dd5199697aabccbd33 Mon Sep 17 00:00:00 2001 From: Nachiket Kapre Date: Tue, 9 Feb 2021 17:04:52 -0500 Subject: [PATCH] default to ns for time unit -- synopsys dc whines --- .../fix_device_route_chan_width_example_script.openfpga | 2 +- .../tasks/fpga_verilog/synthesizable_verilog/config/task.conf | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index c03f2b175..670aabf2c 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -59,7 +59,7 @@ write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE # Write the SDC files for PnR backend # - Turn on every options here -write_pnr_sdc --file ./SDC +write_pnr_sdc --time-unit ns --file ./SDC # Write SDC to disable timing for configure ports write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc diff --git a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf index ea7fb490d..22fe003b9 100644 --- a/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf @@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip #openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=10 +openfpga_vpr_device_layout=auto +openfpga_vpr_route_chan_width=20 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml