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This commit is contained in:
Nachiket Kapre 2021-02-09 11:33:08 -05:00
parent cc74c6268a
commit 87c69460df
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf
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@ -16,12 +16,12 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
#openfpga_vpr_device_layout=2x2
#openfpga_vpr_route_chan_width=10
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=10
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml