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trying fix chan width

This commit is contained in:
Nachiket Kapre 2021-02-09 11:28:19 -05:00
parent 95fe4d7dae
commit cc74c6268a
2 changed files with 3 additions and 384 deletions
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360
openfpga_flow/openfpga_cell_library/verilog/dffsynth.v
View File

@ -1,360 +0,0 @@
//-----------------------------------------------------
// Design Name : D-type Flip-flops
// File Name : ff.v
// Coder : Xifan TANG
//-----------------------------------------------------
//-----------------------------------------------------
// Function : A native D-type flip-flop with single output
//-----------------------------------------------------
module DFFQ (
input CK, // Clock Input
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (posedge CK) begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : A native D-type flip-flop
//-----------------------------------------------------
module DFF (
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (posedge CK) begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - single output
// - asynchronous active high reset
//-----------------------------------------------------
module DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
//-----------------------------------------------------
module DFFR (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active low reset
//-----------------------------------------------------
module DFFRN (
input RSTN, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or negedge RSTN)
if (~RSTN) begin
q_reg <= 1'b0;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high set
//-----------------------------------------------------
module DFFS (
input SET, // Set input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge SET)
if (SET) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active low set
//-----------------------------------------------------
module DFFSN (
input SETN, // Set input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or negedge SETN)
if (~SETN) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// - asynchronous active high set
//-----------------------------------------------------
module DFFSR (
input SET, // set input
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// - asynchronous active high set
//-----------------------------------------------------
module DFFSRQ (
input SET, // set input
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
assign Q = q_reg;
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// - asynchronous active high set
// - scan-chain input
// - a scan-chain enable
//-----------------------------------------------------
module SDFFSR (
input SET, // Set input
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// - scan-chain input
// - a scan-chain enable
//-----------------------------------------------------
module SDFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
assign Q = q_reg;
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// - asynchronous active high set
// - scan-chain input
// - a scan-chain enable
//-----------------------------------------------------
module SDFFSRQ (
input SET, // Set input
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
assign Q = q_reg;
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// - scan-chain input
// - a scan-chain enable
// - a configure enable, when enabled the registered output will
// be released to the Q
//-----------------------------------------------------
module CFGSDFFR (
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
input CFGE, // Configure enable
output Q, // Regular Q output
output CFGQ, // Data Q output which is released when configure enable is activated
output CFGQN // Data Qb output which is released when configure enable is activated
);
//------------Internal Variables--------
reg q_reg;
wire QN;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
assign CFGQ = CFGE ? Q : 1'b0;
assign CFGQN = CFGE ? QN : 1'b1;
endmodule //End Of Module

27
openfpga_flow/tasks/fpga_verilog/synthesizable_verilog/config/task.conf
View File

@ -16,9 +16,12 @@ timeout_each_job = 20*60
fpga_flow=vpr_blif
[OpenFPGA_SHELL]
#openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
#openfpga_vpr_device_layout=2x2
#openfpga_vpr_route_chan_width=10
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
@ -34,27 +37,3 @@ bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
[SCRIPT_PARAM_Fixed_Routing_30]
fix_route_chan_width=30
[SCRIPT_PARAM_Fixed_Routing_40]
fix_route_chan_width=40
[SCRIPT_PARAM_Fixed_Routing_50]
fix_route_chan_width=50
[SCRIPT_PARAM_Fixed_Routing_60]
fix_route_chan_width=60
[SCRIPT_PARAM_Fixed_Routing_70]
fix_route_chan_width=70
[SCRIPT_PARAM_Fixed_Routing_80]
fix_route_chan_width=80
[SCRIPT_PARAM_Fixed_Routing_90]
fix_route_chan_width=90
[SCRIPT_PARAM_Fixed_Routing_100]
fix_route_chan_width=100