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Faster regression test

This commit is contained in:
Baudouin Chauviere 2019-10-05 12:10:55 -06:00
parent 6f7023658e
commit 027272c976
2 changed files with 4 additions and 2 deletions
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2
.travis/script.sh
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@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3
end_section "OpenFPGA.TaskTun"

4
openfpga_flow/tasks/explicit_verilog/config/task.conf
View File

@ -16,6 +16,7 @@ fpga_flow=vpr_blif
[ARCHITECTURES]
arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
#arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif
@ -27,7 +28,7 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT]
fix_route_chan_width=300
min_route_chan_width=1.3
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
@ -39,3 +40,4 @@ vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_x2p_compact_routing_hierarchy=
vpr_fpga_verilog_explicit_mapping=
end_flow_with_test=