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[Arch] Update arch using global reset tile port

This commit is contained in:
tangxifan 2021-01-09 18:04:55 -07:00
parent 7b24da267a
commit 0b74575606
1 changed files with 6 additions and 2 deletions
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8
openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -217,8 +217,12 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="0"/>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0">
<tile name="clb" port="clk"/>
</global_port>
<global_port name="reset" is_reset="true" default_val="0">
<tile name="clb" port="reset"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->