From 0b745756063fca28b3614f18df0a561bc38fcda2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 9 Jan 2021 18:04:55 -0700
Subject: [PATCH] [Arch] Update arch using global reset tile port

---
 ...an_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 0ad0bd1a6..69654611a 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -217,8 +217,12 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
-    <global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="0"/>
+    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0">
+      <tile name="clb" port="clk"/>
+    </global_port>
+    <global_port name="reset" is_reset="true" default_val="0">
+      <tile name="clb" port="reset"/>
+    </global_port>
   </tile_annotations>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->