Adding command to generate verilog file out of yosys run

2021-03-05 04:05:19 -08:00 · 2021-03-05 04:05:19 -08:00 · 2b2acae757
parent 0cbad747a1
commit 2b2acae757
1 changed files with 1 additions and 0 deletions
--- a/openfpga_flow/misc/qlf_yosys.ys
+++ b/openfpga_flow/misc/qlf_yosys.ys
@ -4,3 +4,4 @@ ${READ_VERILOG_FILE}

 synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}

+write_verilog -noattr -nohex ${TOP_MODULE}.v