From 2b2acae75795c850675496d069eda5cebc6bc706 Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Fri, 5 Mar 2021 04:05:19 -0800
Subject: [PATCH] Adding command to generate verilog file out of yosys run

---
 openfpga_flow/misc/qlf_yosys.ys | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys
index 4b861a8c9..638103885 100644
--- a/openfpga_flow/misc/qlf_yosys.ys
+++ b/openfpga_flow/misc/qlf_yosys.ys
@@ -4,3 +4,4 @@ ${READ_VERILOG_FILE}
 
 synth_quicklogic -blif ${OUTPUT_BLIF} -family ${YOSYS_FAMILY} -top ${TOP_MODULE} ${YOSYS_MODE}
 
+write_verilog -noattr -nohex ${TOP_MODULE}.v
\ No newline at end of file