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[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI

This commit is contained in:
tangxifan 2021-03-11 15:25:48 -07:00
parent bb2a02c9ad
commit 366bec232c
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
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@ -40,5 +40,5 @@ bench1_top = adder_8
# The output verilog of yosys is not synthesizable!!!
# Turn off verification for now
# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=