riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

update tileable_routing test

This commit is contained in:
tangxifan 2019-09-18 15:59:32 -06:00
parent e0b253d30a
commit 4e7af5cdc5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/tasks/tileable_routing/config/task.conf
View File

@ -38,7 +38,7 @@ vpr_fpga_verilog_print_user_defined_template=
#vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=
#[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]