diff --git a/openfpga_flow/tasks/tileable_routing/config/task.conf b/openfpga_flow/tasks/tileable_routing/config/task.conf
index 78aa53cb0..3a7f092a6 100644
--- a/openfpga_flow/tasks/tileable_routing/config/task.conf
+++ b/openfpga_flow/tasks/tileable_routing/config/task.conf
@@ -38,7 +38,7 @@ vpr_fpga_verilog_print_user_defined_template=
 #vpr_fpga_verilog_print_report_timing_tcl=
 vpr_fpga_verilog_print_sdc_pnr=
 vpr_fpga_verilog_print_sdc_analysis=
-#vpr_fpga_x2p_compact_routing_hierarchy=
+vpr_fpga_x2p_compact_routing_hierarchy=
 end_flow_with_test=
 
 #[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]