From 4e7af5cdc538934898fec86673bafec2ae38f163 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Sep 2019 15:59:32 -0600 Subject: [PATCH] update tileable_routing test --- openfpga_flow/tasks/tileable_routing/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/tileable_routing/config/task.conf b/openfpga_flow/tasks/tileable_routing/config/task.conf index 78aa53cb0..3a7f092a6 100644 --- a/openfpga_flow/tasks/tileable_routing/config/task.conf +++ b/openfpga_flow/tasks/tileable_routing/config/task.conf @@ -38,7 +38,7 @@ vpr_fpga_verilog_print_user_defined_template= #vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= #[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]