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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile

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tangxifan 2020-11-30 18:11:47 -07:00
parent c7604ab94f
commit 179b0ce304
1 changed files with 1 additions and 0 deletions
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openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf
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@ -36,3 +36,4 @@ bench1_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=