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[Architecture] Bug fix in the SRAM Verilog

This commit is contained in:
tangxifan 2020-09-24 12:26:13 -06:00
parent 9d9cf6ee71
commit 1b13e8ecb1
1 changed files with 7 additions and 7 deletions
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14
openfpga_flow/VerilogNetlists/sram.v
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@ -37,7 +37,7 @@ module SRAM(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule
@ -79,7 +79,7 @@ module SRAMS(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule
@ -121,7 +121,7 @@ module SRAMSN(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule
@ -163,7 +163,7 @@ module SRAMR(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule
@ -205,7 +205,7 @@ module SRAMRN(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule
@ -251,7 +251,7 @@ module SRAMSR(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule
@ -297,7 +297,7 @@ module SRAMSNRN(
assign QN = ~data;
`else
assign Q = 1'bZ;
assign QN = !out;
assign QN = !Q;
`endif
endmodule