riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts

This commit is contained in:
tangxifan 2021-03-16 16:45:57 -06:00
parent 76837e02e6
commit 090f483a11
1 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -481,14 +481,13 @@ def run_yosys_with_abc():
clean_up_and_exit("")
args.K = lut_size
# Yosys script parameter mapping
ys_params = {
"READ_VERILOG_FILE": " \n".join([
ys_params = script_env_vars["PATH"]
ys_params["READ_VERILOG_FILE"] = " \n".join([
"read_verilog -nolatches " + shlex.quote(eachfile)
for eachfile in args.benchmark_files]),
"TOP_MODULE": args.top_module,
"LUT_SIZE": lut_size,
"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
}
for eachfile in args.benchmark_files])
ys_params["TOP_MODULE"] = args.top_module
ys_params["LUT_SIZE"] = lut_size
ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif"
for indx in range(0, len(OpenFPGAArgs), 2):
tmpVar = OpenFPGAArgs[indx][2:].upper()