[Script] Correct bugs in example scripts using default_net_type

openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga

@@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose --default_net_type {OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose --default_net_type ${OPENFPGA_VERILOG_DEFAULT_NET_TYPE}
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists

openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga

@@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template --default_net_type {OPENFPGA_DEFAULT_NET_TYPE} --verbose
+write_fabric_verilog --file ./SRC --include_timing --print_user_defined_template --default_net_type ${OPENFPGA_DEFAULT_NET_TYPE} --verbose
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists