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[Test] Update test case to use dedicated eblif file

This commit is contained in:
tangxifan 2021-02-09 15:51:57 -07:00
parent 1712ee4edb
commit 3ae501a5ea
1 changed files with 1 additions and 1 deletions
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openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf
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@ -26,7 +26,7 @@ openfpga_vpr_circuit_format=eblif
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2_frac_lut4_arith.eblif
[SYNTHESIS_PARAM]
bench0_top = and2