From 3ae501a5eaef5ca293a88d34fbae11a78ab90607 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Feb 2021 15:51:57 -0700 Subject: [PATCH] [Test] Update test case to use dedicated eblif file --- .../fpga_verilog/lut_design/frac_lut4_arith/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf index 62d4ead4b..e855cb3ba 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf @@ -26,7 +26,7 @@ openfpga_vpr_circuit_format=eblif arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2_frac_lut4_arith.eblif [SYNTHESIS_PARAM] bench0_top = and2