riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Regression Test] Move fabric key tests to basic tests

This commit is contained in:
tangxifan 2020-09-29 14:22:23 -06:00
parent ff6570df9d
commit d4d02ab16a
8 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
.travis/basic_reg_test.sh
View File

@ -66,6 +66,15 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
echo -e "Testing Secured FPGA fabrics";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
echo -e "Testing K4 series FPGA";
echo -e "Testing K4N4 with facturable LUTs";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs

6
.travis/fpga_verilog_reg_test.sh
View File

@ -82,12 +82,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin
echo -e "Testing Verilog generation with spy output pads";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
echo -e "Testing Secured FPGA fabrics";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
echo -e "Testing Power-gating designs";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug

0
openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf → openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf
View File

0
openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf → openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf
View File

0
openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf → openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf
View File

0
openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf → openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf
View File

0
openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf → openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf
View File

0
openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf → openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf
View File