From d4d02ab16ae5b4ee8a1d18864abf665d949ff9aa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Sep 2020 14:22:23 -0600 Subject: [PATCH] [Regression Test] Move fabric key tests to basic tests --- .travis/basic_reg_test.sh | 9 +++++++++ .travis/fpga_verilog_reg_test.sh | 6 ------ .../generate_multi_region_vanilla_key/config/task.conf | 0 .../fabric_key/generate_random_key/config/task.conf | 0 .../fabric_key/generate_vanilla_key/config/task.conf | 0 .../fabric_key/load_external_key/config/task.conf | 0 .../load_external_key_cc_fpga/config/task.conf | 0 .../config/task.conf | 0 8 files changed, 9 insertions(+), 6 deletions(-) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/generate_multi_region_vanilla_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/generate_random_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/generate_vanilla_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/load_external_key/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/load_external_key_cc_fpga/config/task.conf (100%) rename openfpga_flow/tasks/{fpga_verilog => basic_tests}/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf (100%) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 4549424d3..8f5961618 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -66,6 +66,15 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench -- echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs +echo -e "Testing Secured FPGA fabrics"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs + + echo -e "Testing K4 series FPGA"; echo -e "Testing K4N4 with facturable LUTs"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index e7582360d..08278e98a 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -82,12 +82,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin echo -e "Testing Verilog generation with spy output pads"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs -echo -e "Testing Secured FPGA fabrics"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs echo -e "Testing Power-gating designs"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/generate_multi_region_vanilla_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/generate_multi_region_vanilla_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/generate_random_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/generate_vanilla_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_cc_fpga/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf b/openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf rename to openfpga_flow/tasks/basic_tests/fabric_key/load_external_key_multi_region_cc_fpga/config/task.conf