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use new simulation setting command in openfpga shell

This commit is contained in:
tangxifan 2020-06-10 15:37:17 -06:00
parent 4a2f6dfae2
commit 96b58dfdbb
15 changed files with 45 additions and 6 deletions
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6
openfpga/src/base/openfpga_link_arch.cpp
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@ -147,9 +147,13 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
* We SHOULD create a new simulation setting for OpenFPGA use only
* Avoid overwrite the raw data achieved when parsing!!!
*/
/* OVERWRITE the simulation setting in openfpga context from the arch
* TODO: This will be removed when openfpga flow is updated
*/
openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
annotate_simulation_setting(g_vpr_ctx.atom(),
openfpga_ctx.net_activity(),
openfpga_ctx.mutable_arch().sim_setting);
openfpga_ctx.mutable_simulation_setting());
/* TODO: should identify the error code from internal function execution */
return CMD_EXEC_SUCCESS;

6
openfpga/src/base/openfpga_sdc.cpp
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@ -88,8 +88,8 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
/* Execute only when sdc is enabled */
if (true == options.generate_sdc_pnr()) {
print_pnr_sdc(options,
1./openfpga_ctx.arch().sim_setting.programming_clock_frequency(),
1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
1./openfpga_ctx.simulation_setting().programming_clock_frequency(),
1./openfpga_ctx.simulation_setting().operating_clock_frequency(),
g_vpr_ctx.device(),
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(),
@ -200,7 +200,7 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
if (true == options.generate_sdc_analysis()) {
print_analysis_sdc(options,
1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
1./openfpga_ctx.simulation_setting().operating_clock_frequency(),
g_vpr_ctx,
openfpga_ctx,
global_ports,

4
openfpga/src/base/openfpga_setup_command.cpp
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@ -365,7 +365,9 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
/* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */
std::vector<ShellCommandId> link_arch_dependent_cmds;
link_arch_dependent_cmds.push_back(read_arch_cmd_id);
link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
/* TODO: This will be uncommented when openfpga flow script is updated
* link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id);
*/
link_arch_dependent_cmds.push_back(vpr_cmd_id);
ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell,
openfpga_setup_cmd_class,

2
openfpga/src/base/openfpga_verilog.cpp
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@ -96,7 +96,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
openfpga_ctx.io_location_map(),
openfpga_ctx.vpr_netlist_annotation(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().sim_setting,
openfpga_ctx.simulation_setting(),
openfpga_ctx.arch().config_protocol.type(),
options);

3
openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE}

3
openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffe
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges

3
openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga
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@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges