From 96b58dfdbbb12c14462d067848ae6038cdce4e95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jun 2020 15:37:17 -0600 Subject: [PATCH] use new simulation setting command in openfpga shell --- openfpga/src/base/openfpga_link_arch.cpp | 6 +++++- openfpga/src/base/openfpga_sdc.cpp | 6 +++--- openfpga/src/base/openfpga_setup_command.cpp | 4 +++- openfpga/src/base/openfpga_verilog.cpp | 2 +- .../configuration_chain_example_script.openfpga | 3 +++ .../duplicated_grid_pin_example_script.openfpga | 3 +++ openfpga_flow/OpenFPGAShellScripts/example_script.openfpga | 3 +++ .../fast_configuration_example_script.openfpga | 3 +++ .../flatten_routing_example_script.openfpga | 3 +++ .../full_testbench_example_script.openfpga | 3 +++ .../generate_fabric_example_script.openfpga | 3 +++ .../generate_testbench_example_script.openfpga | 3 +++ .../implicit_verilog_example_script.openfpga | 3 +++ .../OpenFPGAShellScripts/mcnc_example_script.openfpga | 3 +++ .../sdc_time_unit_example_script.openfpga | 3 +++ 15 files changed, 45 insertions(+), 6 deletions(-) diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index 65aef7cf8..c67619caa 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -147,9 +147,13 @@ int link_arch(OpenfpgaContext& openfpga_ctx, * We SHOULD create a new simulation setting for OpenFPGA use only * Avoid overwrite the raw data achieved when parsing!!! */ + /* OVERWRITE the simulation setting in openfpga context from the arch + * TODO: This will be removed when openfpga flow is updated + */ + openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting; annotate_simulation_setting(g_vpr_ctx.atom(), openfpga_ctx.net_activity(), - openfpga_ctx.mutable_arch().sim_setting); + openfpga_ctx.mutable_simulation_setting()); /* TODO: should identify the error code from internal function execution */ return CMD_EXEC_SUCCESS; diff --git a/openfpga/src/base/openfpga_sdc.cpp b/openfpga/src/base/openfpga_sdc.cpp index 2d44520db..9bcbc26df 100644 --- a/openfpga/src/base/openfpga_sdc.cpp +++ b/openfpga/src/base/openfpga_sdc.cpp @@ -88,8 +88,8 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx, /* Execute only when sdc is enabled */ if (true == options.generate_sdc_pnr()) { print_pnr_sdc(options, - 1./openfpga_ctx.arch().sim_setting.programming_clock_frequency(), - 1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(), + 1./openfpga_ctx.simulation_setting().programming_clock_frequency(), + 1./openfpga_ctx.simulation_setting().operating_clock_frequency(), g_vpr_ctx.device(), openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(), @@ -200,7 +200,7 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx, if (true == options.generate_sdc_analysis()) { print_analysis_sdc(options, - 1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(), + 1./openfpga_ctx.simulation_setting().operating_clock_frequency(), g_vpr_ctx, openfpga_ctx, global_ports, diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index b47cfb97a..e9d759b1f 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -365,7 +365,9 @@ void add_openfpga_setup_commands(openfpga::Shell& shell) { /* The 'link_openfpga_arch' command should NOT be executed before 'vpr' */ std::vector link_arch_dependent_cmds; link_arch_dependent_cmds.push_back(read_arch_cmd_id); - link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id); + /* TODO: This will be uncommented when openfpga flow script is updated + * link_arch_dependent_cmds.push_back(read_sim_setting_cmd_id); + */ link_arch_dependent_cmds.push_back(vpr_cmd_id); ShellCommandId link_arch_cmd_id = add_openfpga_link_arch_command(shell, openfpga_setup_cmd_class, diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 926e0f8d3..58ea20f2e 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -96,7 +96,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, openfpga_ctx.io_location_map(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib, - openfpga_ctx.arch().sim_setting, + openfpga_ctx.simulation_setting(), openfpga_ctx.arch().config_protocol.type(), options); diff --git a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga index 11f3ed295..7492854a2 100644 --- a/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga index bcc8d36e3..83707cf53 100644 --- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga index bcc8d36e3..83707cf53 100644 --- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga index 94e16b906..56d05257c 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index 3210b411f..fa376dbe3 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga index bcc8d36e3..83707cf53 100644 --- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga index ff40f4c76..434c573e1 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga index a426a7833..6fe802168 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga index 579e113a9..021488557 100644 --- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index 3293979ea..ebd6c217c 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffe # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga index 6841eb935..3411f6e87 100644 --- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga @@ -5,6 +5,9 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} +# Read OpenFPGA simulation settings +#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE + # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges